Added all instructions to bitmanip chapter.

Added all instructions in alphabetical order to
bitmanip chapter.

src/b-st-ext.adoc

@@ -1034,3 +1034,107 @@ common operations in cryptographic workloads.
 | <<insns-unzip>>
 
 |===
+
+[#insns,reftext="Instructions (in alphabetical order)"]
+=== Instructions (in alphabetical order)
+include::insns/add_uw.adoc[]
+<<<
+include::insns/andn.adoc[]
+<<<
+include::insns/bclr.adoc[]
+<<<
+include::insns/bclri.adoc[]
+<<<
+include::insns/bext.adoc[]
+<<<
+include::insns/bexti.adoc[]
+<<<
+include::insns/binv.adoc[]
+<<<
+include::insns/binvi.adoc[]
+<<<
+include::insns/bset.adoc[]
+<<<
+include::insns/bseti.adoc[]
+<<<
+include::insns/clmul.adoc[]
+<<<
+include::insns/clmulh.adoc[]
+<<<
+include::insns/clmulr.adoc[]
+<<<
+include::insns/clz.adoc[]
+<<<
+include::insns/clzw.adoc[]
+<<<
+include::insns/cpop.adoc[]
+<<<
+include::insns/cpopw.adoc[]
+<<<
+include::insns/ctz.adoc[]
+<<<
+include::insns/ctzw.adoc[]
+<<<
+include::insns/max.adoc[]
+<<<
+include::insns/maxu.adoc[]
+<<<
+include::insns/min.adoc[]
+<<<
+include::insns/minu.adoc[]
+<<<
+include::insns/orc_b.adoc[]
+<<<
+include::insns/orn.adoc[]
+<<<
+include::insns/pack.adoc[]
+<<<
+include::insns/packh.adoc[]
+<<<
+include::insns/packw.adoc[]
+<<<
+include::insns/rev8.adoc[]
+<<<
+include::insns/revb.adoc[]
+<<<
+include::insns/rol.adoc[]
+<<<
+include::insns/rolw.adoc[]
+<<<
+include::insns/ror.adoc[]
+<<<
+include::insns/rori.adoc[]
+<<<
+include::insns/roriw.adoc[]
+<<<
+include::insns/rorw.adoc[]
+<<<
+include::insns/sext_b.adoc[]
+<<<
+include::insns/sext_h.adoc[]
+<<<
+include::insns/sh1add.adoc[]
+<<<
+include::insns/sh1add_uw.adoc[]
+<<<
+include::insns/sh2add.adoc[]
+<<<
+include::insns/sh2add_uw.adoc[]
+<<<
+include::insns/sh3add.adoc[]
+<<<
+include::insns/sh3add_uw.adoc[]
+<<<
+include::insns/slli_uw.adoc[]
+<<<
+include::insns/unzip.adoc[]
+<<<
+include::insns/xnor.adoc[]
+<<<
+include::insns/xpermb.adoc[]
+<<<
+include::insns/xpermn.adoc[]
+<<<
+include::insns/zext_h.adoc[]
+<<<
+include::insns/zip.adoc[]

src/insns/add_uw.adoc

@@ -0,0 +1,50 @@
+[#insns-add_uw,reftext=Add unsigned word]
+==== add.uw
+
+Synopsis::
+Add unsigned word
+
+Mnemonic::
+add.uw _rd_, _rs1_, _rs2_
+
+
+Pseudoinstructions::
+zext.w _rd_, _rs1_ → add.uw _rd_, _rs1_, zero
+
+Encoding::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  7, name: 0x3b, attr: ['OP-32'] },
+    { bits:  5, name: 'rd' },
+    { bits:  3, name: 0x0, attr: ['ADD.UW'] },
+    { bits:  5, name: 'rs1' },
+    { bits:  5, name: 'rs2' },
+    { bits:  7, name: 0x04, attr: ['ADD.UW'] },
+]}
+....
+
+Description::
+This instruction performs an XLEN-wide addition between _rs2_ and the zero-extended least-significant word of _rs1_.
+
+Operation::
+[source,sail]
+--
+let base = X(rs2);
+let index = EXTZ(X(rs1)[31..0]);
+
+X(rd) = base + index;
+--
+
+Included in::
+[%header,cols="4,2,2"]
+|===
+|Extension
+|Minimum version
+|Lifecycle state
+
+|Zba (<<#zba>>)
+|0.93
+|Frozen
+|===
+

src/insns/andn.adoc

@@ -0,0 +1,47 @@
+[#insns-andn,reftext="AND with inverted operand"]
+==== andn
+
+Synopsis::
+AND with inverted operand
+
+Mnemonic::
+andn _rd_, _rs1_, _rs2_
+
+Encoding::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  7, name: 0x33, attr: ['OP'] },
+    { bits:  5, name: 'rd' },
+    { bits:  3, name: 0x7, attr: ['ANDN']},
+    { bits:  5, name: 'rs1' },
+    { bits:  5, name: 'rs2' },
+    { bits:  7, name: 0x20, attr: ['ANDN'] },
+]}
+....
+
+Description:: 
+This instruction performs the bitwise logical AND operation between _rs1_ and the bitwise inversion of _rs2_.
+
+Operation::
+[source,sail]
+--
+X(rd) = X(rs1) & ~X(rs2);
+--
+
+Included in::
+[%header,cols="4,2,2"]
+|===
+|Extension
+|Minimum version
+|Lifecycle state
+
+|Zbb (<<#zbb>>)
+|0.93
+|Frozen
+
+|Zbkb (<<#zbkb>>)
+|v0.9.4
+|Frozen
+|===
+

src/insns/bclr.adoc

@@ -0,0 +1,45 @@
+[#insns-bclr,reftext="Single-Bit Clear (Register)"]
+==== bclr
+
+Synopsis::
+Single-Bit Clear (Register)
+
+Mnemonic::
+bclr _rd_, _rs1_, _rs2_
+
+Encoding::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  7, name: 0x33, attr: ['OP'] },
+    { bits:  5, name: 'rd' },
+    { bits:  3, name: 0x1, attr: ['BCLR'] },
+    { bits:  5, name: 'rs1' },
+    { bits:  5, name: 'rs2' },
+    { bits:  7, name: 0x24, attr: ['BCLR/BEXT'] },
+]}
+....
+
+Description::
+This instruction returns _rs1_ with a single bit cleared at the index specified in _rs2_.
+The index is read from the lower log2(XLEN) bits of _rs2_.
+
+Operation::
+[source,sail]
+--
+let index = X(rs2) & (XLEN - 1);
+X(rd) = X(rs1) & ~(1 << index)
+--
+
+Included in::
+[%header,cols="4,2,2"]
+|===
+|Extension
+|Minimum version
+|Lifecycle state
+
+|Zbs (<<#zbs>>)
+|0.93
+|Frozen
+|===
+

src/insns/bclri.adoc

@@ -0,0 +1,59 @@
+[#insns-bclri,reftext="Single-Bit Clear (Immediate)"]
+==== bclri
+
+Synopsis::
+Single-Bit Clear (Immediate)
+
+Mnemonic::
+bclri _rd_, _rs1_, _shamt_
+
+Encoding (RV32)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  7, name: 0x13, attr: ['OP-IMM'] },
+    { bits:  5, name: 'rd' },
+    { bits:  3, name: 0x1, attr: ['BCLRI'] },
+    { bits:  5, name: 'rs1' },
+    { bits:  5, name: 'shamt' },
+    { bits:  7, name: 0x24, attr: ['BCLRI'] },
+]}
+....
+
+Encoding (RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  7, name: 0x13, attr: ['OP-IMM'] },
+    { bits:  5, name: 'rd' },
+    { bits:  3, name: 0x1, attr: ['BCLRI'] },
+    { bits:  5, name: 'rs1' },
+    { bits:  6, name: 'shamt' },
+    { bits:  6, name: 0x12, attr: ['BCLRI'] },
+]}
+....
+
+Description::
+This instruction returns _rs1_ with a single bit cleared at the index specified in _shamt_.
+The index is read from the lower log2(XLEN) bits of _shamt_.
+For RV32, the encodings corresponding to shamt[5]=1 are reserved.
+
+Operation::
+[source,sail]
+--
+let index = shamt & (XLEN - 1);
+X(rd) = X(rs1) & ~(1 << index)
+--
+
+Included in::
+[%header,cols="4,2,2"]
+|===
+|Extension
+|Minimum version
+|Lifecycle state
+
+|Zbs (<<#zbs>>)
+|0.93
+|Frozen
+|===
+

src/insns/bext.adoc

@@ -0,0 +1,46 @@
+[#insns-bext,reftext="Single-Bit Extract (Register)"]
+==== bext
+
+Synopsis::
+Single-Bit Extract (Register)
+// Should we describe this as a Set-if-bit-is-set?
+
+Mnemonic::
+bext _rd_, _rs1_, _rs2_
+
+Encoding::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  7, name: 0x33, attr: ['OP'] },
+    { bits:  5, name: 'rd' },
+    { bits:  3, name: 0x5, attr: ['BEXT'] },
+    { bits:  5, name: 'rs1' },
+    { bits:  5, name: 'rs2' },
+    { bits:  7, name: 0x24, attr: ['BCLR/BEXT'] },
+]}
+....
+
+Description::
+This instruction returns a single bit extracted from _rs1_ at the index specified in _rs2_.
+The index is read from the lower log2(XLEN) bits of _rs2_.
+
+Operation::
+[source,sail]
+--
+let index = X(rs2) & (XLEN - 1);
+X(rd) = (X(rs1) >> index) & 1;
+--
+
+Included in::
+[%header,cols="4,2,2"]
+|===
+|Extension
+|Minimum version
+|Lifecycle state
+
+|Zbs (<<#zbs>>)
+|0.93
+|Frozen
+|===
+