Add MECALL backend for RISC-V targets #1017
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romancardenas
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CI tweaked and passes. I will publish the new version of |
AfoHT
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Feb 5, 2025
| @@ -30,6 +30,8 @@ Example: | |||
| - Updated esp32c3 dependency to v0.22.0 | |||
| - Use `riscv-slic` from `crates.io` | |||
| - Remove unused dependency `rtic-monotonics` | |||
| - Updated esp32c3 dependency to v0.25.0 | |||
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Nitpick: Please put these at the top of changelog (like a stack)
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This PR adds a new backend for every RISC-V target. It uses the SLIC philosophy of using a software interrupt controller that multiplexes an interrupt source for every task. However, instead of relying on a CLINT peripheral with software interrupts, it now triggers machine environment call exceptions to do the trick.
Pros of this approach: It is valid for every RISC-V target, regardless of its peripherals. Thus, it is very versatile. It also supports virtually an unlimited number of tasks, as long as they fit in memory. Also, users do not need to bind tasks to interrupt sources manually, as they are synthetically generated when needed.
Cons of this approach: It has more software overhead than using a dedicated physical interrupt controller. For example, for ESP32C3 targets, it may make more sense to use its dedicated ESP32C3 backend.