started test bed, added constants for easier to read code

scarter93 · Jan 29, 2016 · 2ceeda3 · 2ceeda3
1 parent 8244b10
commit 2ceeda3
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Showing 11 changed files with 545 additions and 50 deletions.
diff --git a/alu_16.vhd b/alu_16.vhd
@@ -26,6 +26,20 @@ end entity;
 
 architecture implementation of alu_16 is
 
+CONSTANT ADD : unsigned(3 downto 0) := "0000";
+CONSTANT SUB : unsigned(3 downto 0) := "0001";
+CONSTANT NOT_IN : unsigned(3 downto 0) := "0010";
+CONSTANT AND_IN : unsigned(3 downto 0) := "0011";
+CONSTANT NAND_IN : unsigned(3 downto 0) := "0100";
+CONSTANT OR_IN : unsigned(3 downto 0) := "0101";
+CONSTANT NOR_IN : unsigned(3 downto 0) := "0110";
+CONSTANT XOR_IN : unsigned(3 downto 0) := "0111";
+CONSTANT XNOR_IN : unsigned(3 downto 0) := "1000";
+CONSTANT ASL : unsigned(3 downto 0) := "1001";
+CONSTANT ASR : unsigned(3 downto 0) := "1010";
+CONSTANT LSL : unsigned(3 downto 0) := "1011";
+CONSTANT LSR : unsigned(3 downto 0) := "1100";
+
 Signal input1_temp : std_logic_vector(DATA_WIDTH-1 downto 0);
 --Signal output_t : unsigned(DATA_WIDTH-1 downto 0);
 Signal input1, input2, output : signed(DATA_WIDTH-1 downto 0);
@@ -46,44 +60,44 @@ Process(CLOCK, RESET)
 			out_code <= "0000";
 		elsif rising_edge(CLOCK) then
 			case OPCODE is
-				when "0000" =>
+				when ADD =>
 					output <= input1 + input2;
 					out_code <= in_code;
-				when "0001" =>
+				when SUB =>
 					output <= input1 - input2;
 					out_code <= in_code;
-				when "0010" =>
+				when NOT_IN =>
 					output <= NOT input1;
 					out_code <= in_code;
-				when "0011" =>
+				when AND_IN =>
 					output <= input1 AND input2;
 					out_code <= in_code;
-				when "0100" =>
+				when NAND_IN =>
 					output <= input1 NAND input2;
 					out_code <= in_code;
-				when "0101" =>
+				when OR_IN =>
 					output <= input1 OR input2;
 					out_code <= in_code;
-				when "0110" =>
+				when NOR_IN =>
 					output <= input1 NOR input2;
 					out_code <= in_code;
-				when "0111" =>
+				when XOR_IN =>
 					output <= input1 XOR input2;
 					out_code <= in_code;
-				when "1000" =>
+				when XNOR_IN =>
 					output <= input1 XNOR input2;
 					out_code <= in_code;
-				when "1001" =>
+				when ASL =>
 					output <= shift_left(input1, to_integer(unsigned(input2)));
 					out_code <= in_code;
-				when "1010" =>
+				when ASR =>
 					output <= shift_right(input1, to_integer(unsigned(input2)));
 					out_code <= in_code;
-				when "1011" =>
+				when LSL =>
 					input1_temp <= std_logic_vector(input1);
 					output <= signed(shift_left(unsigned(input1_temp), to_integer(unsigned(input2))));
 					out_code <= in_code;
-				when "1100" =>
+				when LSR =>
 					input1_temp <= std_logic_vector(input1);
 					output <= signed(shift_right(unsigned(input1_temp), to_integer(unsigned(input2))));
 					out_code <= in_code;

diff --git a/alu_16.vhd.bak b/alu_16.vhd.bak
@@ -26,6 +26,20 @@ end entity;
 
 architecture implementation of alu_16 is
 
+CONSTANT ADD : unsigned(3 downto 0) := "0000";
+CONSTANT SUB : unsigned(3 downto 0) := "0001";
+CONSTANT NOT_IN : unsigned(3 downto 0) := "0010";
+CONSTANT ADD_IN : unsigned(3 downto 0) := "0011";
+CONSTANT NAND_IN : unsigned(3 downto 0) := "0100";
+CONSTANT OR_IN : unsigned(3 downto 0) := "0101";
+CONSTANT NOR_IN : unsigned(3 downto 0) := "0110";
+CONSTANT XOR_IN : unsigned(3 downto 0) := "0111";
+CONSTANT XNOR_IN : unsigned(3 downto 0) := "1000";
+CONSTANT ASL : unsigned(3 downto 0) := "1001";
+CONSTANT ASR : unsigned(3 downto 0) := "1010";
+CONSTANT LSL : unsigned(3 downto 0) := "1011";
+CONSTANT LSR : unsigned(3 downto 0) := "1100";
+
 Signal input1_temp : std_logic_vector(DATA_WIDTH-1 downto 0);
 --Signal output_t : unsigned(DATA_WIDTH-1 downto 0);
 Signal input1, input2, output : signed(DATA_WIDTH-1 downto 0);
@@ -46,46 +60,46 @@ Process(CLOCK, RESET)
 			out_code <= "0000";
 		elsif rising_edge(CLOCK) then
 			case OPCODE is
-				when "0000" =>
+				when ADD =>
 					output <= input1 + input2;
 					out_code <= in_code;
-				when "0001" =>
+				when SUB =>
 					output <= input1 - input2;
 					out_code <= in_code;
-				when "0010" =>
+				when NOT_IN =>
 					output <= NOT input1;
 					out_code <= in_code;
-				when "0011" =>
+				when AND_IN =>
 					output <= input1 AND input2;
 					out_code <= in_code;
-				when "0100" =>
+				when NAND_IN =>
 					output <= input1 NAND input2;
 					out_code <= in_code;
-				when "0101" =>
+				when OR_IN =>
 					output <= input1 OR input2;
 					out_code <= in_code;
-				when "0110" =>
+				when NOR_IN =>
 					output <= input1 NOR input2;
 					out_code <= in_code;
-				when "0111" =>
+				when XOR_IN =>
 					output <= input1 XOR input2;
 					out_code <= in_code;
-				when "1000" =>
+				when XNOR_IN =>
 					output <= input1 XNOR input2;
 					out_code <= in_code;
-				when "1001" =>
+				when ASL =>
 					output <= shift_left(input1, to_integer(unsigned(input2)));
 					out_code <= in_code;
-				when "1010" =>
+				when ASR =>
 					output <= shift_right(input1, to_integer(unsigned(input2)));
 					out_code <= in_code;
-				when "1011" =>
+				when LSL =>
 					input1_temp <= std_logic_vector(input1);
-					output <= signed(shift_left(unsigned(input1_temp), to_integer(input2)));
+					output <= signed(shift_left(unsigned(input1_temp), to_integer(unsigned(input2))));
 					out_code <= in_code;
-				when "1100" =>
+				when LSR =>
 					input1_temp <= std_logic_vector(input1);
-					output <= signed(shift_right(unsigned(input1_temp), to_integer(input2)));
+					output <= signed(shift_right(unsigned(input1_temp), to_integer(unsigned(input2))));
 					out_code <= in_code;
 				when others =>
 					output <= "0000000000000000";

diff --git a/alu_tb.vhd b/alu_tb.vhd
@@ -2,27 +2,94 @@
 -- Author: Stephen Carter
 -- Date: 01/28/2016
 
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
 entity alu_testbed is
-  Generic(
+end entity;
+
+architecture testbed of alu_testbed is
+
+Component alu_16 is
+ 	Generic(
 		DATA_WIDTH : integer := 16
 	);
 	Port(
-		OPCODE_T	:	in unsigned(3 downto 0);
-		DATA0_T	:	in signed(DATA_WIDTH-1 downto 0);
-		DATA1_T	:	in signed(DATA_WIDTH-1 downto 0);
+		OPCODE	:	in unsigned(3 downto 0);
+		DATA0	:	in signed(DATA_WIDTH-1 downto 0);
+		DATA1	:	in signed(DATA_WIDTH-1 downto 0);
 
-		CLOCK_T	:	in std_logic;
-		RESET_T	:	in std_logic;
+		CLOCK	:	in std_logic;
+		RESET	:	in std_logic;
+
+		DATA_OUT :	out signed(DATA_WIDTH-1 downto 0);
+		STATUS	:	out unsigned(3 downto 0)
+	);  
+end component;
+
+CONSTANT DATA_WIDTH : integer := 16;
+
+--The input signals with their initial values
+Signal clk, reset_t : std_logic := '0';
+
+Signal input1_t : signed(DATA_WIDTH-1 downto 0) := (others => '0');
+Signal input2_t : signed(DATA_WIDTH-1 downto 0) := (others => '0');
+Signal output_t : signed(DATA_WIDTH-1 downto 0) := (others => '0');
+
+Signal opcode_t : unsigned(3 downto 0);
+Signal status_t : unsigned(3 downto 0);
+
+-- clock input
+CONSTANT clk_period : time := 10 ns;
+
+CONSTANT ADD : unsigned(3 downto 0) := "0000";
+CONSTANT SUB : unsigned(3 downto 0) := "0001";
+CONSTANT NOT_IN : unsigned(3 downto 0) := "0010";
+CONSTANT AND_IN : unsigned(3 downto 0) := "0011";
+CONSTANT NAND_IN : unsigned(3 downto 0) := "0100";
+CONSTANT OR_IN : unsigned(3 downto 0) := "0101";
+CONSTANT NOR_IN : unsigned(3 downto 0) := "0110";
+CONSTANT XOR_IN : unsigned(3 downto 0) := "0111";
+CONSTANT XNOR_IN : unsigned(3 downto 0) := "1000";
+CONSTANT ASL : unsigned(3 downto 0) := "1001";
+CONSTANT ASR : unsigned(3 downto 0) := "1010";
+CONSTANT LSL : unsigned(3 downto 0) := "1011";
+CONSTANT LSR : unsigned(3 downto 0) := "1100";
+
+CONSTANT TEST1_NUM : signed(DATA_WIDTH-1 downto 0) := "0101010101010101"; --
+CONSTANT TEST2_NUM : signed(DATA_WIDTH-1 downto 0) := "1010101010101010"; --
+CONSTANT TEST3_NUM : signed(DATA_WIDTH-1 downto 0) := "1111111100000000"; --
+CONSTANT TEST4_NUM : signed(DATA_WIDTH-1 downto 0) := "0000000011111111"; --
+CONSTANT TEST5_NUM : signed(DATA_WIDTH-1 downto 0) := "1100111100000110"; -- 
+CONSTANT TEST6_NUM : signed(DATA_WIDTH-1 downto 0) := "0100110011110011"; --
 
-		DATA_OUT_T :	out signed(DATA_WIDTH-1 downto 0);
-		STATUS_T	:	out unsigned(3 downto 0)
-	);
-end entity;
 
 
-architecture testbed of alu_testbed is
-
 Begin
+dut: alu_16
+PORT MAP(opcode_t, input1_t, input2_t, clk, reset_t, output_t, status_t);
 
+-- process for clock
+clk_process : Process
+Begin
+	clk <= '0';
+	wait for clk_period/2;
+	clk <= '1';
+	wait for clk_period/2;
+end process;
+
+
+test_alu_process: process
+Begin
+	-- test add and subtract
+	--REPORT "begin test case with double slash comment";
+	--s_input <= test_case_doubleslash(i);
+	--wait for 1 * clk_period;
+	--ASSERT(s_output = '0') REPORT "no comment, and input backslash should be output = '0'" SEVERITY ERROR;
+	--end loop;
+end process;
+
+
 end testbed;
 
diff --git a/alu_tb.vhd.bak b/alu_tb.vhd.bak
@@ -2,21 +2,94 @@
 -- Author: Stephen Carter
 -- Date: 01/28/2016
 
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
 entity alu_testbed is
-  Generic(
+end entity;
+
+architecture testbed of alu_testbed is
+
+Component alu_16 is
+ 	Generic(
 		DATA_WIDTH : integer := 16
 	);
 	Port(
-		OPCODE_T	:	in unsigned(3 downto 0);
-		DATA0_T	:	in signed(DATA_WIDTH-1 downto 0);
-		DATA1_T	:	in signed(DATA_WIDTH-1 downto 0);
+		OPCODE	:	in unsigned(3 downto 0);
+		DATA0	:	in signed(DATA_WIDTH-1 downto 0);
+		DATA1	:	in signed(DATA_WIDTH-1 downto 0);
 
-		CLOCK_T	:	in std_logic;
-		RESET_T	:	in std_logic;
+		CLOCK	:	in std_logic;
+		RESET	:	in std_logic;
+
+		DATA_OUT :	out signed(DATA_WIDTH-1 downto 0);
+		STATUS	:	out unsigned(3 downto 0)
+	);  
+end component;
+
+CONSTANT DATA_WIDTH : integer := 16;
+
+--The input signals with their initial values
+Signal clk, reset_t : std_logic := '0';
+
+Signal input1_t : signed(DATA_WIDTH-1 downto 0) := (others => '0');
+Signal input2_t : signed(DATA_WIDTH-1 downto 0) := (others => '0');
+Signal output_t : signed(DATA_WIDTH-1 downto 0) := (others => '0');
+
+Signal opcode_t : unsigned(3 downto 0);
+Signal status_t : unsigned(3 downto 0);
+
+-- clock input
+CONSTANT clk_period : time := 10 ns;
+
+CONSTANT ADD : unsigned(3 downto 0) := "0000";
+CONSTANT SUB : unsigned(3 downto 0) := "0001";
+CONSTANT NOT_IN : unsigned(3 downto 0) := "0010";
+CONSTANT AND_IN : unsigned(3 downto 0) := "0011";
+CONSTANT NAND_IN : unsigned(3 downto 0) := "0100";
+CONSTANT OR_IN : unsigned(3 downto 0) := "0101";
+CONSTANT NOR_IN : unsigned(3 downto 0) := "0110";
+CONSTANT XOR_IN : unsigned(3 downto 0) := "0111";
+CONSTANT XNOR_IN : unsigned(3 downto 0) := "1000";
+CONSTANT ASL : unsigned(3 downto 0) := "1001";
+CONSTANT ASR : unsigned(3 downto 0) := "1010";
+CONSTANT LSL : unsigned(3 downto 0) := "1011";
+CONSTANT LSR : unsigned(3 downto 0) := "1100";
+
+CONSTANT TEST1_NUM : signed(DATA_WIDTH-1 downto 0) := "0101010101010101"; --
+CONSTANT TEST2_NUM : signed(DATA_WIDTH-1 downto 0) := "1010101010101010"; --
+CONSTANT TEST3_NUM : signed(DATA_WIDTH-1 downto 0) := "1111111100000000"; --
+CONSTANT TEST4_NUM : signed(DATA_WIDTH-1 downto 0) := "0000000011111111"; --
+CONSTANT TEST5_NUM : signed(DATA_WIDTH-1 downto 0) := "1100111100000110"; -- 
+CONSTANT TEST6_NUM : signed(DATA_WIDTH-1 downto 0) := "0100110011110011"; --
+
+
+
+Begin
+dut: alu_16
+PORT MAP(opcode_t, input1_t, input2_t, clk, reset_t, output_t, status_t);
+
+-- process for clock
+clk_process : Process
+Begin
+	clk <= '0';
+	wait for clk_period/2;
+	clk <= '1';
+	wait for clk_period/2;
+end process;
+
+
+test_alu_process: process
+Begin
+	-- test add and subtract
+	REPORT "begin test case with double slash comment";
+	s_input <= test_case_doubleslash(i);
+	wait for 1 * clk_period;
+	ASSERT(s_output = '0') REPORT "no comment, and input backslash should be output = '0'" SEVERITY ERROR;
+	end loop;
+end process;
 
-		DATA_OUT_T :	out signed(DATA_WIDTH-1 downto 0);
-		STATUS_T	:	out unsigned(3 downto 0)
-	);
-end entity;
 
+end testbed;