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scx_utils/scx_layered: code modernisation/simplifications. #1239

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Jan 23, 2025
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2 changes: 1 addition & 1 deletion rust/scx_utils/src/topology.rs
Original file line number Diff line number Diff line change
Expand Up @@ -506,7 +506,7 @@ fn create_insert_cpu(
core_id: *core_id,
llc_id: *llc_id,
node_id: node.id,
package_id: package_id,
package_id,
}),
);

Expand Down
4 changes: 2 additions & 2 deletions scheds/rust/scx_layered/src/layer_core_growth.rs
Original file line number Diff line number Diff line change
Expand Up @@ -133,7 +133,7 @@ struct LayerCoreOrderGenerator<'a> {
impl<'a> LayerCoreOrderGenerator<'a> {
fn rotate_layer_offset(&self, vec: &'a mut Vec<usize>) -> &Vec<usize> {
let num_cores = self.topo.all_cores.len();
let chunk = num_cores.div_ceil(self.layer_specs.len()) as usize;
let chunk = num_cores.div_ceil(self.layer_specs.len());
vec.rotate_right((chunk * self.layer_idx).min(num_cores));
vec
}
Expand All @@ -156,7 +156,7 @@ impl<'a> LayerCoreOrderGenerator<'a> {
self.rotate_layer_offset(&mut core_order);

for node in self.topo.nodes.values() {
for (_, llc) in &node.llcs {
for llc in node.llcs.values() {
let llc_cores = llc.cores.len();
let rot = rot_by(llc_cores + (self.layer_idx << 1), llc_cores);
if is_left {
Expand Down
10 changes: 5 additions & 5 deletions scheds/rust/scx_layered/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -876,7 +876,7 @@ impl Stats {
.layers
.iter()
.take(self.nr_layers)
.map(|layer| layer.slice_ns / 1000 as u64)
.map(|layer| layer.slice_ns / 1000_u64)
.collect();

let cur_layer_usages = Self::read_layer_usages(&cpu_ctxs, self.nr_layers);
Expand Down Expand Up @@ -969,7 +969,7 @@ impl Layer {
if cpus_range.0 > cpus_range.1 || cpus_range.1 == 0 {
bail!("invalid cpus_range {:?}", cpus_range);
}
if nodes.len() == 0 && llcs.len() == 0 {
if nodes.is_empty() && llcs.is_empty() {
allowed_cpus.set_all();
} else {
// build up the cpus bitset
Expand Down Expand Up @@ -1008,21 +1008,21 @@ impl Layer {
common: LayerCommon { nodes, llcs, .. },
..
} => {
if nodes.len() == 0 && llcs.len() == 0 {
if nodes.is_empty() && llcs.is_empty() {
allowed_cpus.set_all();
} else {
// build up the cpus bitset
for (node_id, node) in &topo.nodes {
// first do the matching for nodes
if nodes.contains(node_id) {
for (&id, _cpu) in &node.all_cpus {
for &id in node.all_cpus.keys() {
allowed_cpus.set_cpu(id)?;
}
}
// next match on any LLCs
for (llc_id, llc) in &node.llcs {
if llcs.contains(llc_id) {
for (&id, _cpu) in &llc.all_cpus {
for &id in llc.all_cpus.keys() {
allowed_cpus.set_cpu(id)?;
}
}
Expand Down
30 changes: 13 additions & 17 deletions tools/scxtop/src/app.rs
Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,7 @@ impl<'a> App<'a> {
active_perf_events,
available_events: default_events,
available_perf_events_list,
num_perf_events: num_perf_events,
num_perf_events,
events_list_size: 1,
selected_event: 0,
non_hw_event_active: false,
Expand Down Expand Up @@ -583,8 +583,7 @@ impl<'a> App<'a> {
let llc_iter = self
.llc_data
.values()
.map(|llc_data| llc_data.event_data_immut(self.active_event.event.clone()))
.flatten()
.flat_map(|llc_data| llc_data.event_data_immut(self.active_event.event.clone()))
.collect::<Vec<u64>>();
let stats = VecStats::new(&llc_iter, true, true, true, None);

Expand Down Expand Up @@ -683,8 +682,7 @@ impl<'a> App<'a> {
let node_iter = self
.node_data
.values()
.map(|node_data| node_data.event_data_immut(self.active_event.event.clone()))
.flatten()
.flat_map(|node_data| node_data.event_data_immut(self.active_event.event.clone()))
.collect::<Vec<u64>>();
let stats = VecStats::new(&node_iter, true, true, true, None);

Expand Down Expand Up @@ -918,8 +916,7 @@ impl<'a> App<'a> {
let dsq_global_iter = self
.dsq_data
.values()
.map(|dsq_data| dsq_data.event_data_immut(event.clone()))
.flatten()
.flat_map(|dsq_data| dsq_data.event_data_immut(event.clone()))
.collect::<Vec<u64>>();
let stats = VecStats::new(&dsq_global_iter, true, true, true, None);
let sample_rate = self.skel.maps.data_data.sample_rate;
Expand Down Expand Up @@ -993,8 +990,7 @@ impl<'a> App<'a> {
let dsq_global_iter = self
.dsq_data
.values()
.map(|dsq_data| dsq_data.event_data_immut(event.clone()))
.flatten()
.flat_map(|dsq_data| dsq_data.event_data_immut(event.clone()))
.collect::<Vec<u64>>();
let stats = VecStats::new(&dsq_global_iter, true, true, true, None);
let sample_rate = self.skel.maps.data_data.sample_rate;
Expand Down Expand Up @@ -1066,8 +1062,7 @@ impl<'a> App<'a> {
.dsq_data
.iter()
.filter(|(_dsq_id, event_data)| event_data.data.contains_key(&event.clone()))
.map(|(_dsq_id, event_data)| event_data.event_data_immut(event.clone()))
.flatten()
.flat_map(|(_dsq_id, event_data)| event_data.event_data_immut(event.clone()))
.collect::<Vec<u64>>();

let stats = VecStats::new(&vtime_global_iter, true, true, true, None);
Expand Down Expand Up @@ -1136,8 +1131,7 @@ impl<'a> App<'a> {
let dsq_global_iter = self
.dsq_data
.values()
.map(|dsq_data| dsq_data.event_data_immut(event.clone()))
.flatten()
.flat_map(|dsq_data| dsq_data.event_data_immut(event.clone()))
.collect::<Vec<u64>>();
let stats = VecStats::new(&dsq_global_iter, true, true, true, None);

Expand Down Expand Up @@ -1259,8 +1253,9 @@ impl<'a> App<'a> {
.cpu_data
.values()
.filter(|cpu_data| cpu_data.node == node.id)
.map(|cpu_data| cpu_data.event_data_immut(self.active_event.event.clone()))
.flatten()
.flat_map(|cpu_data| {
cpu_data.event_data_immut(self.active_event.event.clone())
})
.collect::<Vec<u64>>();
let stats = VecStats::new(&node_iter, true, true, true, None);

Expand Down Expand Up @@ -1366,8 +1361,9 @@ impl<'a> App<'a> {
.cpu_data
.values()
.filter(|cpu_data| cpu_data.node == node.id)
.map(|cpu_data| cpu_data.event_data_immut(self.active_event.event.clone()))
.flatten()
.flat_map(|cpu_data| {
cpu_data.event_data_immut(self.active_event.event.clone())
})
.collect::<Vec<u64>>();
let stats = VecStats::new(&node_iter, true, true, true, None);

Expand Down