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add test
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seekworser committed Aug 9, 2019
1 parent 52e3835 commit 935aaf4
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3 changes: 3 additions & 0 deletions .gitignore
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Expand Up @@ -6,3 +6,6 @@
*.ngc
*.ngd
*.pcf
test/*
!test/.keep
*.o
1 change: 1 addition & 0 deletions Readme.md
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Expand Up @@ -29,6 +29,7 @@ or other commands shown in below.
- map
- par
- bitgen
- test [-e entity]

# Notification

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12 changes: 10 additions & 2 deletions src/project.yaml
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@@ -1,11 +1,19 @@
src_files:
- filename: sample.vhd
- file_name: sample.vhd
language: vhdl
library: work
entity_names:
- sample

test_files:
- file_name: test_sample.vhd
entity_names:
- test_sample
- test_sample2

ucf_file: sample_ucf.ucf

top_module: sample_project
top_module: sample

part:
device: xc6slx9
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34 changes: 16 additions & 18 deletions src/sample.vhd
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@@ -1,25 +1,23 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sample_project is
entity sample is
Port (
A : out STD_LOGIC_VECTOR (15 downto 0);
B : out STD_LOGIC_VECTOR (15 downto 0);
C : out STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC
A : out std_logic_vector (8 downto 0);
clk : in std_logic
);
end sample_project;
end sample;

architecture Behavioral of sample_project is
signal counter : STD_LOGIC_VECTOR(47 downto 0) := (others => '0');
begin count: process(clk)
begin if rising_edge(clk) then
architecture behavior of sample is
signal counter : std_logic_vector(21 downto 0) := (others => '0');
begin
count: process(clk)
begin
if rising_edge(clk) then
counter <= counter+1;
end if;
end process;
A <= counter(35 downto 20);
B <= counter(31 downto 16);
C <= counter(15 downto 0);
end Behavioral;
A <= counter(21 downto 13);
end behavior;
78 changes: 39 additions & 39 deletions src/sample_ucf.ucf
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Expand Up @@ -38,45 +38,45 @@ NET A(5) LOC="P66" | IOSTANDARD=LVTTL;
NET A(6) LOC="P67" | IOSTANDARD=LVTTL; # A6
NET A(7) LOC="P75" | IOSTANDARD=LVTTL; # A7
NET A(8) LOC="P79" | IOSTANDARD=LVTTL; # A8
NET A(9) LOC="P81" | IOSTANDARD=LVTTL; # A9
NET A(10) LOC="P83" | IOSTANDARD=LVTTL; # A10
NET A(11) LOC="P85" | IOSTANDARD=LVTTL; # A11
NET A(12) LOC="P88" | IOSTANDARD=LVTTL; # A12
NET A(13) LOC="P93" | IOSTANDARD=LVTTL; # A13
NET A(14) LOC="P98" | IOSTANDARD=LVTTL; # A14
NET A(15) LOC="P100" | IOSTANDARD=LVTTL; # A15
NET B(0) LOC="P99" | IOSTANDARD=LVTTL; # B0
NET B(1) LOC="P97" | IOSTANDARD=LVTTL; # B1
NET B(2) LOC="P92" | IOSTANDARD=LVTTL; # B2
NET B(3) LOC="P87" | IOSTANDARD=LVTTL; # B3
NET B(4) LOC="P84" | IOSTANDARD=LVTTL; # B4
NET B(5) LOC="P82" | IOSTANDARD=LVTTL; # B5
NET B(6) LOC="P80" | IOSTANDARD=LVTTL; # B6
NET B(7) LOC="P78" | IOSTANDARD=LVTTL; # B7
NET B(8) LOC="P74" | IOSTANDARD=LVTTL; # B8
NET B(9) LOC="P95" | IOSTANDARD=LVTTL; # B9
NET B(10) LOC="P62" | IOSTANDARD=LVTTL; # B10
NET B(11) LOC="P59" | IOSTANDARD=LVTTL; # B11
NET B(12) LOC="P57" | IOSTANDARD=LVTTL; # B12
NET B(13) LOC="P55" | IOSTANDARD=LVTTL; # B13
NET B(14) LOC="P50" | IOSTANDARD=LVTTL; # B14
NET B(15) LOC="P47" | IOSTANDARD=LVTTL; # B15
NET C(0) LOC="P114" | IOSTANDARD=LVTTL; # C0
NET C(1) LOC="P115" | IOSTANDARD=LVTTL; # C1
NET C(2) LOC="P116" | IOSTANDARD=LVTTL; # C2
NET C(3) LOC="P117" | IOSTANDARD=LVTTL; # C3
NET C(4) LOC="P118" | IOSTANDARD=LVTTL; # C4
NET C(5) LOC="P119" | IOSTANDARD=LVTTL; # C5
NET C(6) LOC="P120" | IOSTANDARD=LVTTL; # C6
NET C(7) LOC="P121" | IOSTANDARD=LVTTL; # C7
NET C(8) LOC="P123" | IOSTANDARD=LVTTL; # C8
NET C(9) LOC="P124" | IOSTANDARD=LVTTL; # C9
NET C(10) LOC="P126" | IOSTANDARD=LVTTL; # C10
NET C(11) LOC="P127" | IOSTANDARD=LVTTL; # C11
NET C(12) LOC="P131" | IOSTANDARD=LVTTL; # C12
NET C(13) LOC="P132" | IOSTANDARD=LVTTL; # C13
NET C(14) LOC="P133" | IOSTANDARD=LVTTL; # C14
NET C(15) LOC="P134" | IOSTANDARD=LVTTL; # C15
# NET A(9) LOC="P81" | IOSTANDARD=LVTTL; # A9
# NET A(10) LOC="P83" | IOSTANDARD=LVTTL; # A10
# NET A(11) LOC="P85" | IOSTANDARD=LVTTL; # A11
# NET A(12) LOC="P88" | IOSTANDARD=LVTTL; # A12
# NET A(13) LOC="P93" | IOSTANDARD=LVTTL; # A13
# NET A(14) LOC="P98" | IOSTANDARD=LVTTL; # A14
# NET A(15) LOC="P100" | IOSTANDARD=LVTTL; # A15
# NET B(0) LOC="P99" | IOSTANDARD=LVTTL; # B0
# NET B(1) LOC="P97" | IOSTANDARD=LVTTL; # B1
# NET B(2) LOC="P92" | IOSTANDARD=LVTTL; # B2
# NET B(3) LOC="P87" | IOSTANDARD=LVTTL; # B3
# NET B(4) LOC="P84" | IOSTANDARD=LVTTL; # B4
# NET B(5) LOC="P82" | IOSTANDARD=LVTTL; # B5
# NET B(6) LOC="P80" | IOSTANDARD=LVTTL; # B6
# NET B(7) LOC="P78" | IOSTANDARD=LVTTL; # B7
# NET B(8) LOC="P74" | IOSTANDARD=LVTTL; # B8
# NET B(9) LOC="P95" | IOSTANDARD=LVTTL; # B9
# NET B(10) LOC="P62" | IOSTANDARD=LVTTL; # B10
# NET B(11) LOC="P59" | IOSTANDARD=LVTTL; # B11
# NET B(12) LOC="P57" | IOSTANDARD=LVTTL; # B12
# NET B(13) LOC="P55" | IOSTANDARD=LVTTL; # B13
# NET B(14) LOC="P50" | IOSTANDARD=LVTTL; # B14
# NET B(15) LOC="P47" | IOSTANDARD=LVTTL; # B15
# NET C(0) LOC="P114" | IOSTANDARD=LVTTL; # C0
# NET C(1) LOC="P115" | IOSTANDARD=LVTTL; # C1
# NET C(2) LOC="P116" | IOSTANDARD=LVTTL; # C2
# NET C(3) LOC="P117" | IOSTANDARD=LVTTL; # C3
# NET C(4) LOC="P118" | IOSTANDARD=LVTTL; # C4
# NET C(5) LOC="P119" | IOSTANDARD=LVTTL; # C5
# NET C(6) LOC="P120" | IOSTANDARD=LVTTL; # C6
# NET C(7) LOC="P121" | IOSTANDARD=LVTTL; # C7
# NET C(8) LOC="P123" | IOSTANDARD=LVTTL; # C8
# NET C(9) LOC="P124" | IOSTANDARD=LVTTL; # C9
# NET C(10) LOC="P126" | IOSTANDARD=LVTTL; # C10
# NET C(11) LOC="P127" | IOSTANDARD=LVTTL; # C11
# NET C(12) LOC="P131" | IOSTANDARD=LVTTL; # C12
# NET C(13) LOC="P132" | IOSTANDARD=LVTTL; # C13
# NET C(14) LOC="P133" | IOSTANDARD=LVTTL; # C14
# NET C(15) LOC="P134" | IOSTANDARD=LVTTL; # C15
# NET SDRAM_ADDR(0) LOC="P140" | IOSTANDARD=LVTTL; # SDRAM_ADDR0
# NET SDRAM_ADDR(1) LOC="P139" | IOSTANDARD=LVTTL; # SDRAM_ADDR1
# NET SDRAM_ADDR(2) LOC="P138" | IOSTANDARD=LVTTL; # SDRAM_ADDR2
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67 changes: 67 additions & 0 deletions src/test_sample.vhd
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@@ -0,0 +1,67 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity test_sample is
end test_sample;

architecture behavior of test_sample is
component sample is
Port (
clk: in std_logic;
A: out std_logic_vector (8 downto 0)
);
end component;
signal clk: std_logic;
signal A: std_logic_vector (8 downto 0);
begin
u1: sample port map(
clk => clk,
A => A
);
process
begin
for i in 0 to 1000000 loop
clk <= '1';
wait for 16.25 ns;
clk <= '0';
wait for 16.25 ns;
end loop;
wait;
end process;
end behavior;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity test_sample2 is
end test_sample2;

architecture behavior of test_sample2 is
component sample is
Port (
clk: in std_logic;
A: out std_logic_vector (8 downto 0)
);
end component;
signal clk: std_logic;
signal A: std_logic_vector (8 downto 0);
begin
u1: sample port map(
clk => clk,
A => A
);
process
begin
for i in 0 to 1000 loop
clk <= '1';
wait for 16.25 us;
clk <= '0';
wait for 16.25 us;
end loop;
wait;
end process;
end behavior;
49 changes: 46 additions & 3 deletions tasks.py
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Expand Up @@ -21,7 +21,7 @@ def create_project_file():
for item in get_project_parameter(SRC_FILES_KEY):
language = set_default_on_keyerror(item, LANGUAGE_KEY, LANGUAGE_DEFAULT)
library = set_default_on_keyerror(item, LIBRARY_KEY, LIBRARY_DEFAULT)
filename = item[FILENAME_KEY]
filename = item[FILE_NAME_KEY]
content += "{language:s} {library:s} .{srcdir:s}{filename:s}\n".format(
language=language,
library=library,
Expand Down Expand Up @@ -150,6 +150,44 @@ def bitgen(c):
))
return

def gdhl_compile(c, file_name, entity_names):
with c.cd("{testdir:s}".format(testdir=TESTDIR)):
c.run("ghdl -a --ieee=synopsys .{srcdir:s}{file_name:s}".format(
srcdir=SRCDIR,
file_name=file_name,
))
for entity_name in entity_names:
c.run("ghdl -e --ieee=synopsys {entity_name:s}".format(
srcdir=SRCDIR,
entity_name=entity_name,
))
return

def ghdl_test_runner(c, entity_name):
with c.cd("{testdir:s}".format(testdir=TESTDIR)):
c.run("ghdl -r {entity_name:s} --vcd={entity_name:s}.vcd".format(
entity_name=entity_name,
))
return

def ghdl_clean(c):
c.run("rm {testdir:s}*.o {testdir:s}*.cf".format(testdir=TESTDIR))

@invoke.task(iterable=["entity_name"])
def test(c, entity_name):
if not entity_name:
entity_name = []
for item in get_project_parameter(TEST_FILES_KEY):
entity_name += item[ENTITY_NAMES_KEY]
for item in get_project_parameter(SRC_FILES_KEY):
gdhl_compile(c, item[FILE_NAME_KEY], item[ENTITY_NAMES_KEY])
for item in get_project_parameter(TEST_FILES_KEY):
gdhl_compile(c, item[FILE_NAME_KEY], item[ENTITY_NAMES_KEY])
for item in entity_name:
ghdl_test_runner(c, item)
ghdl_clean(c)
return

@invoke.task
def build(c):
xst(c)
Expand All @@ -163,15 +201,20 @@ def build(c):
OUTDIR = "./out/"
SRCDIR = "./src/"
LOGDIR = "./log/"
TESTDIR = "./test/"
PROJECT_YAML_FILE_NAME = SRCDIR + "project.yaml"

LANGUAGE_DEFAULT = "vhdl"
LIBRARY_DEFAULT = "work"

SRC_FILES_KEY = "src_files"
LANGUAGE_KEY = "language"
LIBRARY_KEY = "library"
FILENAME_KEY = "filename"
SRC_FILES_KEY = "src_files"
FILE_NAME_KEY = "file_name"

TEST_FILES_KEY = "test_files"
ENTITY_NAMES_KEY = "entity_names"

TOP_MODULE_KEY = "top_module"
PART_KEY = "part"
ARCHITECTURE_KEY = "architecture"
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