change all characters to lower case.

src/sample.vhd

@@ -4,8 +4,8 @@ use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
 entity sample is
-    Port (
-        A : out  std_logic_vector (8 downto 0);
+    port (
+        a : out  std_logic_vector (8 downto 0);
         clk : in std_logic
     );
 end sample;
@@ -19,5 +19,5 @@ begin
             counter <= counter+1;
         end if;
     end process;
-    A <= counter(21 downto 13);
+    a <= counter(21 downto 13);
 end behavior;

src/test_sample.vhd

@@ -8,17 +8,17 @@ end test_sample;
 
 architecture behavior of test_sample is
     component sample is
-        Port (
+        port (
             clk: in std_logic;
-            A: out std_logic_vector (8 downto 0)
+            a: out std_logic_vector (8 downto 0)
         );
     end component;
     signal clk: std_logic;
-    signal A: std_logic_vector (8 downto 0);
+    signal a: std_logic_vector (8 downto 0);
 begin 
     u1: sample port map(
         clk => clk,
-        A => A
+        a => a
     );
     process
     begin
@@ -42,17 +42,17 @@ end test_sample2;
 
 architecture behavior of test_sample2 is
     component sample is
-        Port (
+        port (
             clk: in std_logic;
-            A: out std_logic_vector (8 downto 0)
+            a: out std_logic_vector (8 downto 0)
         );
     end component;
     signal clk: std_logic;
-    signal A: std_logic_vector (8 downto 0);
+    signal a: std_logic_vector (8 downto 0);
 begin 
     u1: sample port map(
         clk => clk,
-        A => A
+        a => a
     );
     process
     begin