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Improving iolib cells #83

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merged 9 commits into from
Oct 28, 2024
Merged

Improving iolib cells #83

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a8327c9
Making input buffer "bullet proof"
aolofsson Oct 26, 2024
7152e56
Making bidir cell more robust
aolofsson Oct 26, 2024
997f82e
Updating side logic for new io cells
aolofsson Oct 26, 2024
6ff7f95
Updating padring with new pe/ps cells
aolofsson Oct 26, 2024
8380d64
Removing signal
aolofsson Oct 26, 2024
6e8c766
Adding back ctrls to la_ioinput
aolofsson Oct 28, 2024
4e59d6a
Adding back ctrl signals to la_ioinput
aolofsson Oct 28, 2024
603ca6a
Adding missing CFGW
aolofsson Oct 28, 2024
79a8998
add back ie to input cell and fix typo
gadfort Oct 28, 2024
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126 changes: 122 additions & 4 deletions lambdalib/iolib/rtl/la_iobidir.v
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Original file line number Diff line number Diff line change
Expand Up @@ -26,14 +26,132 @@ module la_iobidir
output z, // output to core
input ie, // input enable, 1 = active
input oe, // output enable, 1 = active
input pe, // pull enable, 1 = enable
input ps, // pull select, 1 = pullup, 0 = pulldown
inout [RINGW-1:0] ioring, // generic io ring
input [CFGW-1:0] cfg // generic config interface
);

// to core
assign z = ie ? pad : 1'b0;
assign z = ie ? pad : 1'b0;
assign pad = oe ? a : 1'bz;

// to pad
assign pad = oe ? a : 1'bz;
`ifndef VERILATOR
rnmos #1 (pad, vssio, pe & ~ps); // weak pulldown
rnmos #1 (pad, vddio, pe & ps); // weak pullup
`endif

endmodule

//######################################################################
// MINIMAL TESTBENCH
//######################################################################

`ifdef TB_LA_IOBIDIR

module tb();

parameter CFGW = 16;
parameter RINGW = 8;

localparam PERIOD = 10;
localparam TIMEOUT = PERIOD * 200;

reg drive;
reg data;

// control block
initial
begin
$timeformat(-9, 0, " ns", 20);
$dumpfile("dump.vcd");
$dumpvars(0, tb);
#(TIMEOUT)
$finish;
end

// test program
initial
begin
// inactive
a = 1'bx;
ie = 1'b0;
oe = 1'b0;
pe = 1'b0;
ps = 1'b0;
cfg = 'b0;
drive = 1'b0;
data = 1'b0;
// with pulldown
#(PERIOD)
pe = 1'b1;
ps = 1'b0;
// with pullup
#(PERIOD)
ps = 1'b1;
// driven input with pullup
#(PERIOD)
ie = 1'b1;
drive = 1'b1;
data = 1'b0;
#(PERIOD)
data = 1'b1;
// output
#(PERIOD)
drive = 1'b0;
oe = 1'b1;
a = 1'b0;
#(PERIOD)
a = 1'b1;
// conflict
drive = 1'b1;
data = 1'b0;
end

assign vss = 1'b0;
assign vssio = 1'b0;
assign vdd = 1'b1;
assign vddio = 1'b1;

assign pad = drive ? data : 1'bz;

/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg a;
reg [CFGW-1:0] cfg;
reg ie;
reg oe;
reg pe;
reg ps;
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [RINGW-1:0] ioring;
wire pad;
wire vdd;
wire vddio;
wire vss;
wire vssio;
wire z;
// End of automatics

la_iobidir
la_iobidir(/*AUTOINST*/
// Outputs
.z (z),
// Inouts
.pad (pad),
.vdd (vdd),
.vss (vss),
.vddio (vddio),
.vssio (vssio),
.ioring (ioring[RINGW-1:0]),
// Inputs
.a (a),
.ie (ie),
.oe (oe),
.pe (pe),
.ps (ps),
.cfg (cfg[CFGW-1:0]));

endmodule
`endif
33 changes: 21 additions & 12 deletions lambdalib/iolib/rtl/la_ioinput.v
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Expand Up @@ -10,25 +10,34 @@
*************************************************************************/
module la_ioinput
#(
parameter PROP = "DEFAULT", // cell property
parameter PROP = "DEFAULT", // "FIXED" ignores all ctrl inputs
parameter SIDE = "NO", // "NO", "SO", "EA", "WE"
parameter CFGW = 16, // width of core config bus
parameter CFGW = 16, // width of config bus
parameter RINGW = 8 // width of io ring
)
(// io pad signals
inout pad, // input pad
inout vdd, // core supply
inout vss, // core ground
inout vddio, // io supply
inout vssio, // io ground
inout pad, // input pad
inout vdd, // core supply
inout vss, // core ground
inout vddio, // io supply
inout vssio, // io ground
// core facing signals
output z, // output to core
input ie, // input enable, 1 = active
inout [RINGW-1:0] ioring, // generic ioring interface
input [CFGW-1:0] cfg // generic config interface
output z, // output to core
input ie, // input enable, 1 = active
input pe, // pull enable, 1=enable
input ps, // pull select, 1=pullup, 0=pulldown
input [CFGW-1:0] cfg, // generic config interface
// io ring
inout [RINGW-1:0] ioring // generic ioring interface
);

// to core
assign z = ie ? pad : 1'b0;

`ifndef VERILATOR
if(PROP!="FIXED") begin
rnmos #1 (pad, vssio, pe & ~ps); // weak pulldown
rnmos #1 (pad, vddio, pe & ps); // weak pullup
end
`endif

endmodule
26 changes: 26 additions & 0 deletions lambdalib/padring/rtl/la_iopadring.v
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Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,8 @@ module la_iopadring
input [NO_NPINS-1:0] no_a, // input from core
input [NO_NPINS-1:0] no_ie, // input enable, 1 = active
input [NO_NPINS-1:0] no_oe, // output enable, 1 = active
input [NO_NPINS-1:0] no_pe, // pull enable, 1 = enable
input [NO_NPINS-1:0] no_ps, // pull select, 1 = pullup
input [NO_NPINS*CFGW-1:0] no_cfg, // generic config interface
inout [NO_NSECTIONS-1:0] no_vdd, // core supply
inout [NO_NSECTIONS-1:0] no_vddio, // io/analog supply
Expand All @@ -75,6 +77,8 @@ module la_iopadring
input [EA_NPINS-1:0] ea_a,
input [EA_NPINS-1:0] ea_ie,
input [EA_NPINS-1:0] ea_oe,
input [EA_NPINS-1:0] ea_pe,
input [EA_NPINS-1:0] ea_ps,
input [EA_NPINS*CFGW-1:0] ea_cfg,
inout [EA_NSECTIONS-1:0] ea_vdd,
inout [EA_NSECTIONS-1:0] ea_vddio,
Expand All @@ -88,6 +92,8 @@ module la_iopadring
input [SO_NPINS-1:0] so_a,
input [SO_NPINS-1:0] so_ie,
input [SO_NPINS-1:0] so_oe,
input [SO_NPINS-1:0] so_pe,
input [SO_NPINS-1:0] so_ps,
input [SO_NPINS*CFGW-1:0] so_cfg,
inout [SO_NSECTIONS-1:0] so_vdd,
inout [SO_NSECTIONS-1:0] so_vddio,
Expand All @@ -101,6 +107,8 @@ module la_iopadring
input [WE_NPINS-1:0] we_a,
input [WE_NPINS-1:0] we_ie,
input [WE_NPINS-1:0] we_oe,
input [WE_NPINS-1:0] we_pe,
input [WE_NPINS-1:0] we_ps,
input [WE_NPINS*CFGW-1:0] we_cfg,
inout [WE_NSECTIONS-1:0] we_vdd,
inout [WE_NSECTIONS-1:0] we_vddio,
Expand Down Expand Up @@ -133,6 +141,8 @@ module la_iopadring
.a (no_a),
.ie (no_ie),
.oe (no_oe),
.pe (no_pe),
.ps (no_ps),
.cfg (no_cfg));

// EAST
Expand All @@ -158,6 +168,8 @@ module la_iopadring
.a (ea_a),
.ie (ea_ie),
.oe (ea_oe),
.pe (ea_pe),
.ps (ea_ps),
.cfg (ea_cfg));

// WEST
Expand All @@ -183,6 +195,8 @@ module la_iopadring
.a (we_a),
.ie (we_ie),
.oe (we_oe),
.pe (we_pe),
.ps (we_ps),
.cfg (we_cfg));

// SOUTH
Expand All @@ -208,6 +222,8 @@ module la_iopadring
.a (so_a),
.ie (so_ie),
.oe (so_oe),
.pe (so_pe),
.ps (so_ps),
.cfg (so_cfg));

endmodule
Expand Down Expand Up @@ -298,6 +314,8 @@ module tb();
.\(.*\)_a ({NPINS{1'b0}}),
.\(.*\)_ie ({NPINS{1'b1}}),
.\(.*\)_oe ({NPINS{1'b0}}),
.\(.*\)_ps ({NPINS{1'b0}}),
.\(.*\)_pe ({NPINS{1'b1}}),
.\(.*\)_cfg ({CFGW*NPINS{1'b0}}),
.\(.*\)_vdd (\1_vdd[NSECTIONS-1:0]),
.\(.*\)_vddio (\1_vddio[NSECTIONS-1:0]),
Expand Down Expand Up @@ -364,18 +382,26 @@ module tb();
.no_a ({NPINS{1'b0}}), // Templated
.no_ie ({NPINS{1'b1}}), // Templated
.no_oe ({NPINS{1'b0}}), // Templated
.no_pe ({NPINS{1'b1}}), // Templated
.no_ps ({NPINS{1'b0}}), // Templated
.no_cfg ({CFGW*NPINS{1'b0}}), // Templated
.ea_a ({NPINS{1'b0}}), // Templated
.ea_ie ({NPINS{1'b1}}), // Templated
.ea_oe ({NPINS{1'b0}}), // Templated
.ea_pe ({NPINS{1'b1}}), // Templated
.ea_ps ({NPINS{1'b0}}), // Templated
.ea_cfg ({CFGW*NPINS{1'b0}}), // Templated
.so_a ({NPINS{1'b0}}), // Templated
.so_ie ({NPINS{1'b1}}), // Templated
.so_oe ({NPINS{1'b0}}), // Templated
.so_pe ({NPINS{1'b1}}), // Templated
.so_ps ({NPINS{1'b0}}), // Templated
.so_cfg ({CFGW*NPINS{1'b0}}), // Templated
.we_a ({NPINS{1'b0}}), // Templated
.we_ie ({NPINS{1'b1}}), // Templated
.we_oe ({NPINS{1'b0}}), // Templated
.we_pe ({NPINS{1'b1}}), // Templated
.we_ps ({NPINS{1'b0}}), // Templated
.we_cfg ({CFGW*NPINS{1'b0}})); // Templated

endmodule
Expand Down
18 changes: 12 additions & 6 deletions lambdalib/padring/rtl/la_ioside.v
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
/*****************************************************************************
/**************************************************************************
* Function: Padring Side Module
* Copyright: Lambda Project Authors. All rights Reserved.
* License: MIT (see LICENSE file in Lambda repository)
Expand All @@ -7,7 +7,7 @@
*
* See "../README.md" for complete information
*
* -------------------------------------------------------------------------
* -----------------------------------------------------------------------
*
*
* CELLMAP[39:0] = {PROP[7:0],SECTION[7:0],CELL[7:0],COMP[7:0],PIN[7:0]}
Expand All @@ -27,7 +27,7 @@
* CELLMAP[79:0] = {{NULL, NULL, LA_RXDIFF, PIN_RXN, PIN_RXP}
* {NULL, NULL, LA_BIDIR, NULL, PIN_IO0}}
*
****************************************************************************/
*************************************************************************/

module la_ioside
#(// per side parameters
Expand All @@ -48,6 +48,8 @@ module la_ioside
input [NPINS-1:0] a, // input from core
input [NPINS-1:0] ie, // input enable, 1 = active
input [NPINS-1:0] oe, // output enable, 1 = active
input [NPINS-1:0] pe, // pull enable, 1 = enable
input [NPINS-1:0] ps, // pull select, 1 = pullup
input [NPINS*CFGW-1:0] cfg, // generic config interface
// supplies/ring (per cell)
inout vss, // common ground
Expand All @@ -72,11 +74,13 @@ module la_ioside
.RINGW(RINGW))
i0 (// pad
.pad(pad[CELLMAP[(i*40)+:8]]),
// core signalas
// core signals
.z(zp[CELLMAP[(i*40)+:8]]),
.a(a[CELLMAP[(i*40)+:8]]),
.ie(ie[CELLMAP[(i*40)+:8]]),
.oe(oe[CELLMAP[(i*40)+:8]]),
.pe(pe[CELLMAP[(i*40)+:8]]),
.ps(ps[CELLMAP[(i*40)+:8]]),
.cfg(cfg[CELLMAP[(i*40)+:8]*CFGW+:CFGW]),
// supplies
.vss(vss),
Expand All @@ -95,9 +99,11 @@ module la_ioside
.RINGW(RINGW))
i0 (// pad
.pad(pad[CELLMAP[(i*40)+:8]]),
// core signalas
// core signals
.z(zp[CELLMAP[(i*40)+:8]]),
.ie(ie[CELLMAP[(i*40)+:8]]),
.pe(pe[CELLMAP[(i*40)+:8]]),
.ps(ps[CELLMAP[(i*40)+:8]]),
.cfg(cfg[CELLMAP[(i*40)+:8]*CFGW+:CFGW]),
// supplies
.vss(vss),
Expand All @@ -115,7 +121,7 @@ module la_ioside
.RINGW(RINGW))
i0 (// pad
.pad(pad[CELLMAP[(i*40)+:8]]),
// core signalas
// core signals
.aio(aio[CELLMAP[(i*40)+:8]*3+:3]),
// supplies
.vss(vss),
Expand Down