Merge pull request #27 from slaclab/optimizedDigAsicstreamAxi

Optimized dig asicstream axi
slaclab · May 2, 2024 · 3f7fb39 · 3f7fb39
2 parents 22b0b2f + 2b3caba
commit 3f7fb39
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Showing 2 changed files with 4 additions and 2 deletions.
diff --git a/firmware/python/ePix320kM/_Root.py b/firmware/python/ePix320kM/_Root.py
@@ -118,7 +118,7 @@ def __init__(   self,
             # Create configuration stream
             stream = pyrogue.interfaces.stream.Variable(root=self)
 
-            # Create StreamWriter with the configuration stream included as channel 1
+            # Create StreamWriter with the configuration stream included as channel 5
             self.dataWriter = pyrogue.utilities.fileio.StreamWriter(configStream={5: stream})
             self.add(self.dataWriter)               
 
@@ -401,6 +401,8 @@ def start(self, **kwargs):
     def enableAllAsics(self, enable) :
         for batcherIndex in range(self.numOfAsics) :
             self.enableAsic(batcherIndex, enable)
+        time.sleep(0.1)
+
 
     def enableAsic(self, batcherIndex, enable) :
         getattr(self.App.AsicTop, f"BatcherEventBuilder{batcherIndex}").Blowoff.set(not enable)

diff --git a/firmware/submodules/epix-hr-leap-common b/firmware/submodules/epix-hr-leap-common
+52 −62		python/epix_hr_leap_common/_DigitalAsicStreamAxi.py
+1 −0		shared/rtl/AsicTop.vhd
+124 −46		shared/rtl/DigitalAsicStreamAxiV2.vhd