adding new FPGA target for apps/hal (esl-epfl#555)

specs-feup · Jul 17, 2024 · 5df30f4 · 5df30f4
1 parent 608691c
commit 5df30f4
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Showing 11 changed files with 30 additions and 18 deletions.
diff --git a/sw/applications/example_ams_peripheral/main.c b/sw/applications/example_ams_peripheral/main.c
@@ -10,7 +10,7 @@
 #include "ams_regs.h"
 #include "mmio.h"
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
   #error ( "This app does NOT work on the FPGA as it relies on the simulator testbench" )
 #endif
 

diff --git a/sw/applications/example_dma_multichannel/main.c b/sw/applications/example_dma_multichannel/main.c
@@ -136,7 +136,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif TARGET_IS_FPGA && PRINTF_IN_FPGA
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)

diff --git a/sw/applications/example_freertos_blinky/main.c b/sw/applications/example_freertos_blinky/main.c
@@ -116,7 +116,7 @@
 
 /* The rate at which data is sent to the queue.  The 200ms value is converted
 to ticks using the pdMS_TO_TICKS() macro. */
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
 #define mainQUEUE_SEND_FREQUENCY_MS			pdMS_TO_TICKS( 200 )
 #else
 #define mainQUEUE_SEND_FREQUENCY_MS			pdMS_TO_TICKS( 3 )
@@ -148,7 +148,7 @@ or 0 to run the more comprehensive test and demo application. */
 #endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
 
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
     #define GPIO_LD5_R  15
     #define GPIO_LD5_B  16
 	#define GPIO_LD5_G  17

diff --git a/sw/applications/example_gpio_intr/main.c b/sw/applications/example_gpio_intr/main.c
@@ -41,7 +41,7 @@
 #endif
 
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
     #define GPIO_TB_OUT 8
     #define GPIO_TB_IN  9
     #define GPIO_INTR  GPIO_INTR_9

diff --git a/sw/applications/example_i2s/main.c b/sw/applications/example_i2s/main.c
@@ -34,7 +34,7 @@
 #include "i2s_structs.h"
 
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
 #define I2S_TEST_BATCH_SIZE    128
 #define I2S_TEST_BATCHES      16
 #define I2S_CLK_DIV           8
@@ -173,7 +173,7 @@ void setup()
 int main(int argc, char *argv[]) {
     bool success = true;
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
     for (uint32_t i = 0; i < 0x10000; i++) asm volatile("nop");
 #endif
     PRINTF("I2S DEMO\r\n\r");
@@ -182,7 +182,7 @@ int main(int argc, char *argv[]) {
 
     //PRINTF("Setup done!\r\n\r");
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
 
 
     for (uint32_t i = 0; i < I2S_WAIT_CYCLES; i++) asm volatile("nop");

diff --git a/sw/applications/example_power_manager/main.c b/sw/applications/example_power_manager/main.c
@@ -41,7 +41,7 @@ static rv_timer_t timer_2_3;
 static const uint64_t kTickFreqHz = 1000 * 1000; // 1 MHz
 static power_manager_t power_manager;
 
-#ifndef TARGET_PYNQ_Z2
+#ifndef TARGET_IS_FPGA
     #define GPIO_TB_OUT 30
     #define GPIO_TB_IN  31
     #define GPIO_INTR  GPIO_INTR_31
@@ -73,7 +73,7 @@ int main(int argc, char *argv[])
     uint32_t reset_off, reset_on, switch_off, switch_on, iso_off, iso_on;
 
     // Setup pads
-#ifndef TARGET_PYNQ_Z2
+#ifndef TARGET_IS_FPGA
     pad_control_t pad_control;
     pad_control.base_addr = mmio_region_from_addr((uintptr_t)PAD_CONTROL_START_ADDRESS);
     pad_control_set_mux(&pad_control, (ptrdiff_t)(PAD_CONTROL_PAD_MUX_I2C_SCL_REG_OFFSET), 1);
@@ -196,12 +196,16 @@ int main(int argc, char *argv[])
     tgt_src.size_du = TEST_DATA_SIZE;
     tgt_src.trig = DMA_TRIG_MEMORY;
     tgt_src.type = DMA_DATA_TYPE_WORD;
+    tgt_src.env = NULL;
+    tgt_src.inc_d2_du = 0;
 
     tgt_dst.ptr = (uint8_t *)copied_data_4B;
     tgt_dst.inc_du = 1;
     tgt_dst.size_du = TEST_DATA_SIZE;
     tgt_dst.trig = DMA_TRIG_MEMORY;
     tgt_dst.type = DMA_DATA_TYPE_WORD;
+    tgt_dst.env = NULL;
+    tgt_dst.inc_d2_du = 0;
 
     trans.src = &tgt_src;
     trans.dst = &tgt_dst;
@@ -212,14 +216,19 @@ int main(int argc, char *argv[])
     trans.win_du = 0;
     trans.sign_ext = 0;
     trans.end = DMA_TRANS_END_INTR;
+    trans.dim = DMA_DIM_CONF_1D;
+    trans.pad_top_du = 0;
+    trans.pad_bottom_du = 0;
+    trans.pad_left_du = 0;
+    trans.pad_right_du = 0;
 
-    trans.flags = 0x0;                                                                        
+    trans.flags = 0x0;
     res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
     res = dma_load_transaction(&trans);
     res = dma_launch(&trans);
 
-    while (!dma_is_ready(0))                   
-    {                                         
+    while (!dma_is_ready(0))
+    {
         CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
         if (dma_is_ready(0) == 0)
         {             
@@ -239,11 +248,11 @@ int main(int argc, char *argv[])
         }
     }
 
-#ifndef TARGET_PYNQ_Z2
+#ifndef TARGET_IS_FPGA
     // Power-gate and wake-up due to plic GPIO
 
     gpio_assign_irq_handler( GPIO_INTR_31, &gpio_handler_in );
-	
+
     bool state = false;
     plic_irq_set_priority(GPIO_INTR_31, 1);
     plic_irq_set_enabled(GPIO_INTR_31, kPlicToggleEnabled);

diff --git a/sw/applications/example_sdk_spi_flash/main.c b/sw/applications/example_sdk_spi_flash/main.c
@@ -30,13 +30,13 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif TARGET_IS_FPGA && PRINTF_IN_FPGA
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
 #endif
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
     #define USE_SPI_FLASH
 #endif
 

diff --git a/sw/applications/example_spi_host_dma_power_gate/main.c b/sw/applications/example_spi_host_dma_power_gate/main.c
@@ -17,7 +17,7 @@
 #include "power_manager.h"
 #include "x-heep.h"
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
     #define USE_SPI_FLASH
 #endif
 

diff --git a/sw/device/target/nexys-a7-100t/x-heep.h b/sw/device/target/nexys-a7-100t/x-heep.h
@@ -15,6 +15,7 @@ extern "C" {
 #define REFERENCE_CLOCK_Hz 15*1000*1000
 #define UART_BAUDRATE 9600
 #define TARGET_NEXYS_A7_100T 1
+#define TARGET_IS_FPGA 1
 
 /**
  * As the hw is configurable, we can have setups with different number of

diff --git a/sw/device/target/pynq-z2/x-heep.h b/sw/device/target/pynq-z2/x-heep.h
@@ -15,6 +15,7 @@ extern "C" {
 #define REFERENCE_CLOCK_Hz 15*1000*1000
 #define UART_BAUDRATE 9600
 #define TARGET_PYNQ_Z2 1
+#define TARGET_IS_FPGA 1
 
 /**
  * As the hw is configurable, we can have setups with different number of

diff --git a/sw/device/target/zcu104/x-heep.h b/sw/device/target/zcu104/x-heep.h
@@ -14,6 +14,7 @@ extern "C" {
 #define REFERENCE_CLOCK_Hz 15*1000*1000
 #define UART_BAUDRATE 9600
 #define TARGET_ZCU104 1
+#define TARGET_IS_FPGA 1
 
 /**
  * As the hw is configurable, we can have setups with different number of