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squared-studio: Crafting VLSI Excellence

Welcome to squared-studio! As an open-source platform, squared-studio covers everything from RTL design to verification. This is the perfect space to learn, grow, master, innovate, and share ideas while developing skills in VLSI Frontend RTL Design & Verification. We are committed to building a community where we can collaborate and share ideas to innovate and improve these technologies beyond what is currently possible.

🎯 Our Mission: At squared-studio, we're not just learning skills; we're cultivating mastery. Through this platform, we want everyone to reach that expert level where they feel confident and skilled. At the same time, we want it to be an open-source knowledge platform for everyone who is interested in learning about VLSI technology.

🚀 What's Next: We have a bunch of exciting projects coming up soon. Stay tuned for updates and join us to be a part of the journey.

🤝 Join Us: Whether you want to showcase your unique VLSI design or are simply curious to learn more about VLSI, squared-studio is open to you. Your interest in VLSI is the only prerequisite.

Feel free to reach out at [email protected], and let's collaborate to revolutionize the VLSI landscape for tomorrow.

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  1. common common Public

    SystemVerilog IP design & verification

    SystemVerilog 6

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Showing 10 of 13 repositories
  • SkillVerse Public
    squared-studio/SkillVerse’s past year of commit activity
    1 0 0 0 Updated Mar 6, 2025
  • maverickOne Public
    squared-studio/maverickOne’s past year of commit activity
    SystemVerilog 1 MIT 0 4 1 Updated Jan 24, 2025
  • uart Public
    squared-studio/uart’s past year of commit activity
    Makefile 0 MIT 0 2 0 Updated Jan 9, 2025
  • testing Public
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    Makefile 0 MIT 0 1 0 Updated Jan 9, 2025
  • risc-v-core Public
    squared-studio/risc-v-core’s past year of commit activity
    SystemVerilog 1 MIT 0 4 0 Updated Jan 9, 2025
  • clocking Public
    squared-studio/clocking’s past year of commit activity
    SystemVerilog 0 MIT 0 0 0 Updated Jan 9, 2025
  • axi Public
    squared-studio/axi’s past year of commit activity
    SystemVerilog 0 MIT 0 8 0 Updated Jan 9, 2025
  • risc-v-model Public
    squared-studio/risc-v-model’s past year of commit activity
    C 0 MIT 0 0 0 Updated Jan 9, 2025
  • common Public

    SystemVerilog IP design & verification

    squared-studio/common’s past year of commit activity
    SystemVerilog 6 MIT 0 19 0 Updated Jan 9, 2025
  • sv-genesis Public
    squared-studio/sv-genesis’s past year of commit activity
    Makefile 0 MIT 0 0 0 Updated Jan 9, 2025

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