Moved FSM state definition before jinja if statement

stdefeber · Aug 14, 2024 · 33963a2 · 33963a2
1 parent 10ad9bb
commit 33963a2
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Showing 2 changed files with 5 additions and 4 deletions.
diff --git a/corsair/templates/wb2lb_verilog.j2 b/corsair/templates/wb2lb_verilog.j2
@@ -31,12 +31,12 @@ module {{ module_name }} #(
     output [DATA_W-1:0] wb_dat_o,
     output              wb_ack_o  
 );
-{% if regmap_embed %}
-
 
 reg [1:0] c_state;
 parameter s_idle=0, s_write=1, s_read=2;
 
+{% if regmap_embed %}
+
 wire              wready;
 wire [ADDR_W-1:0] waddr;
 wire [DATA_W-1:0] wdata;

diff --git a/corsair/templates/wb2lb_vhdl.j2 b/corsair/templates/wb2lb_vhdl.j2
@@ -86,12 +86,13 @@ port(
 );
 end {{ module_name }};
 architecture arch_imp of {{ module_name }} is
-{% macro wb_signals(regmap_embed=False) %}
-    {% if regmap_embed %}
 
 type fsm_states is (s_idle, s_write, s_read);
 signal c_state : fsm_states;
 
+{% macro wb_signals(regmap_embed=False) %}
+    {% if regmap_embed %}
+
 signal wready : std_logic;
 signal waddr  : std_logic_vector(ADDR_W-1 downto 0);
 signal wdata  : std_logic_vector(DATA_W-1 downto 0);