update deps

.vscode/settings.json

@@ -1,6 +1,6 @@
 {
   "rust.all_targets": false,
-  "rust.target": "thumbv7em-none-eabi",
+  "rust.target": "thumbv7m-none-eabi",
   "rust.all_features": false,
   "rust.features": [
     "rtic",
@@ -10,7 +10,7 @@
   "rust-analyzer.checkOnSave.allTargets": false,
   "rust-analyzer.checkOnSave.extraArgs": [
       "--target",
-      "thumbv7em-none-eabi"
+      "thumbv7m-none-eabi"
   ],
   "rust-analyzer.cargo.features": [
     "rtic",

Cargo.toml

@@ -18,15 +18,15 @@ features = ["stm32f103", "rt"]
 default-target = "x86_64-unknown-linux-gnu"
 
 [dependencies]
-cortex-m = "0.7.4"
+cortex-m = "0.7.6"
 cortex-m-rt = "0.7.1"
 nb = "1"
-stm32f1 = "0.14.0"
+stm32f1 = "0.15.1"
 embedded-dma = "0.2.0"
 bxcan = "0.7"
 void = { default-features = false, version = "1.0.2" }
 embedded-hal = { features = ["unproven"], version = "0.2.7" }
-fugit = "0.3.5"
+fugit = "0.3.6"
 fugit-timer = "0.1.3"
 rtic-monotonic = { version = "1.0", optional = true }
 bitflags = "1.3.2"
@@ -37,12 +37,12 @@ optional = true
 
 [dev-dependencies]
 panic-halt = "0.2.0"
-panic-semihosting = "0.5.6"
-panic-itm = "0.4.1"
-cortex-m-rtic = "1.0.0"
-cortex-m-semihosting = "0.3.7"
-heapless = "0.7.10"
-mfrc522 = "0.2.0"
+panic-semihosting = "0.6.0"
+panic-itm = "0.4.2"
+cortex-m-rtic = "1.1.3"
+cortex-m-semihosting = "0.5.0"
+heapless = "0.7.16"
+mfrc522 = "0.3.0"
 usb-device = "0.2.8"
 usbd-serial = "0.1.1"
 unwrap-infallible = "0.1.5"

examples/i2c-bme280/Cargo.toml

@@ -8,15 +8,15 @@ edition = "2018"
 publish = false
 
 [dependencies]
-bme280 = "0.2.1"
-cortex-m-semihosting = "0.3.3"
-panic-semihosting = "0.5.2"
-cortex-m-rt = "0.6.8"
-cortex-m = "0.6.0"
+bme280 = "0.3.0"
+cortex-m-semihosting = "0.5.0"
+panic-semihosting = "0.6.0"
+cortex-m-rt = "0.7.1"
+cortex-m = "0.7.6"
 
 [dependencies.stm32f1xx-hal]
 path = "../.."
-version = "0.7.0"
+version = "0.9.0"
 features = ["stm32f103", "rt", "stm32-usbd"]
 
 [profile.dev]

examples/i2c-bme280/src/main.rs

@@ -21,10 +21,9 @@
 use cortex_m_semihosting::hprintln;
 use panic_semihosting as _;
 
-use bme280::BME280;
+use bme280::i2c::BME280;
 use cortex_m_rt::entry;
 use stm32f1xx_hal::{
-    delay::Delay,
     i2c::{BlockingI2c, DutyCycle, Mode},
     pac,
     prelude::*,
@@ -40,7 +39,7 @@ fn main() -> ! {
     // Take ownership over the raw flash and rcc devices and convert them into the corresponding
     // HAL structs
     let mut flash = dp.FLASH.constrain();
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
     let mut afio = dp.AFIO.constrain();
     // Freeze the configuration of all the clocks in the system and store the frozen frequencies in
     // `clocks`
@@ -80,23 +79,23 @@ fn main() -> ! {
 
     // The Adafruit boards have address 0x77 without closing the jumper on the back, the BME280 lib connects to 0x77 with `new_secondary`, use
     // `new_primary` for 0x76 if you close the jumper/solder bridge.
-    let mut bme280 = BME280::new_secondary(i2c, Delay::new(cp.SYST, &clocks));
+    let mut bme280 = BME280::new_secondary(i2c, cp.SYST.delay(&clocks));
     bme280
         .init()
         .map_err(|error| {
-            hprintln!("Could not initialize bme280, Error: {:?}", error).unwrap();
+            hprintln!("Could not initialize bme280, Error: {:?}", error);
             panic!();
         })
         .unwrap();
     loop {
         match bme280.measure() {
             Ok(measurements) => {
-                hprintln!("Relative Humidity = {}%", measurements.humidity).unwrap();
-                hprintln!("Temperature = {} deg C", measurements.temperature).unwrap();
-                hprintln!("Pressure = {} pascals", measurements.pressure).unwrap();
+                hprintln!("Relative Humidity = {}%", measurements.humidity);
+                hprintln!("Temperature = {} deg C", measurements.temperature);
+                hprintln!("Pressure = {} pascals", measurements.pressure)
             }
             Err(error) => {
-                hprintln!("Could not read bme280 due to error: {:?}", error).unwrap();
+                hprintln!("Could not read bme280 due to error: {:?}", error);
             }
         }
     }

src/rcc.rs

@@ -495,12 +495,12 @@ impl Default for Config {
         Self {
             hse: None,
             pllmul: None,
-            hpre: HPre::DIV1,
-            ppre1: PPre::DIV1,
-            ppre2: PPre::DIV1,
+            hpre: HPre::Div1,
+            ppre1: PPre::Div1,
+            ppre2: PPre::Div1,
             #[cfg(any(feature = "stm32f103", feature = "connectivity"))]
-            usbpre: UsbPre::DIV1_5,
-            adcpre: AdcPre::DIV2,
+            usbpre: UsbPre::Div15,
+            adcpre: AdcPre::Div2,
         }
     }
 }
@@ -509,38 +509,38 @@ impl Default for Config {
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
 pub enum HPre {
     /// SYSCLK not divided
-    DIV1 = 7,
+    Div1 = 7,
     /// SYSCLK divided by 2
-    DIV2 = 8,
+    Div2 = 8,
     /// SYSCLK divided by 4
-    DIV4 = 9,
+    Div4 = 9,
     /// SYSCLK divided by 8
-    DIV8 = 10,
+    Div8 = 10,
     /// SYSCLK divided by 16
-    DIV16 = 11,
+    Div16 = 11,
     /// SYSCLK divided by 64
-    DIV64 = 12,
+    Div64 = 12,
     /// SYSCLK divided by 128
-    DIV128 = 13,
+    Div128 = 13,
     /// SYSCLK divided by 256
-    DIV256 = 14,
+    Div256 = 14,
     /// SYSCLK divided by 512
-    DIV512 = 15,
+    Div512 = 15,
 }
 
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
 #[repr(u8)]
 pub enum PPre {
     /// HCLK not divided
-    DIV1 = 3,
+    Div1 = 3,
     /// HCLK divided by 2
-    DIV2 = 4,
+    Div2 = 4,
     /// HCLK divided by 4
-    DIV4 = 5,
+    Div4 = 5,
     /// HCLK divided by 8
-    DIV8 = 6,
+    Div8 = 6,
     /// HCLK divided by 16
-    DIV16 = 7,
+    Div16 = 7,
 }
 
 #[cfg(feature = "stm32f103")]
@@ -582,18 +582,18 @@ impl Config {
 
         let hpre_bits = if let Some(hclk) = cfgr.hclk {
             match sysclk / hclk {
-                0..=1 => HPre::DIV1,
-                2 => HPre::DIV2,
-                3..=5 => HPre::DIV4,
-                6..=11 => HPre::DIV8,
-                12..=39 => HPre::DIV16,
-                40..=95 => HPre::DIV64,
-                96..=191 => HPre::DIV128,
-                192..=383 => HPre::DIV256,
-                _ => HPre::DIV512,
+                0..=1 => HPre::Div1,
+                2 => HPre::Div2,
+                3..=5 => HPre::Div4,
+                6..=11 => HPre::Div8,
+                12..=39 => HPre::Div16,
+                40..=95 => HPre::Div64,
+                96..=191 => HPre::Div128,
+                192..=383 => HPre::Div256,
+                _ => HPre::Div512,
             }
         } else {
-            HPre::DIV1
+            HPre::Div1
         };
 
         let hclk = if hpre_bits as u8 >= 0b1100 {
@@ -610,23 +610,23 @@ impl Config {
             36_000_000
         };
         let ppre1_bits = match (hclk + pclk1 - 1) / pclk1 {
-            0 | 1 => PPre::DIV1,
-            2 => PPre::DIV2,
-            3..=5 => PPre::DIV4,
-            6..=11 => PPre::DIV8,
-            _ => PPre::DIV16,
+            0 | 1 => PPre::Div1,
+            2 => PPre::Div2,
+            3..=5 => PPre::Div4,
+            6..=11 => PPre::Div8,
+            _ => PPre::Div16,
         };
 
         let ppre2_bits = if let Some(pclk2) = cfgr.pclk2 {
             match hclk / pclk2 {
-                0..=1 => PPre::DIV1,
-                2 => PPre::DIV2,
-                3..=5 => PPre::DIV4,
-                6..=11 => PPre::DIV8,
-                _ => PPre::DIV16,
+                0..=1 => PPre::Div1,
+                2 => PPre::Div2,
+                3..=5 => PPre::Div4,
+                6..=11 => PPre::Div8,
+                _ => PPre::Div16,
             }
         } else {
-            PPre::DIV1
+            PPre::Div1
         };
 
         let ppre2 = 1 << (ppre2_bits as u8 - 0b011);
@@ -635,19 +635,19 @@ impl Config {
         // usbpre == false: divide clock by 1.5, otherwise no division
         #[cfg(any(feature = "stm32f103", feature = "connectivity"))]
         let usbpre = match (hse, pllmul_bits, sysclk) {
-            (Some(_), Some(_), 72_000_000) => UsbPre::DIV1_5,
-            _ => UsbPre::DIV1,
+            (Some(_), Some(_), 72_000_000) => UsbPre::Div15,
+            _ => UsbPre::Div1,
         };
 
         let apre_bits = if let Some(adcclk) = cfgr.adcclk {
             match pclk2 / adcclk {
-                0..=2 => AdcPre::DIV2,
-                3..=4 => AdcPre::DIV4,
-                5..=7 => AdcPre::DIV6,
-                _ => AdcPre::DIV8,
+                0..=2 => AdcPre::Div2,
+                3..=4 => AdcPre::Div4,
+                5..=7 => AdcPre::Div6,
+                _ => AdcPre::Div8,
             }
         } else {
-            AdcPre::DIV8
+            AdcPre::Div8
         };
 
         Self {
@@ -731,12 +731,12 @@ fn rcc_config_usb() {
     let config_expected = Config {
         hse: Some(8_000_000),
         pllmul: Some(4),
-        hpre: HPre::DIV1,
-        ppre1: PPre::DIV2,
-        ppre2: PPre::DIV1,
+        hpre: HPre::Div1,
+        ppre1: PPre::Div2,
+        ppre2: PPre::Div1,
         #[cfg(any(feature = "stm32f103", feature = "connectivity"))]
-        usbpre: UsbPre::DIV1,
-        adcpre: AdcPre::DIV8,
+        usbpre: UsbPre::Div1,
+        adcpre: AdcPre::Div8,
     };
     assert_eq!(config, config_expected);
 

src/serial.rs

@@ -385,8 +385,8 @@ fn apply_config<USART: Instance>(config: Config, clocks: &Clocks) {
         });
         use crate::pac::usart1::cr1::PS_A;
         w.ps().variant(match config.parity {
-            Parity::ParityOdd => PS_A::ODD,
-            _ => PS_A::EVEN,
+            Parity::ParityOdd => PS_A::Odd,
+            _ => PS_A::Even,
         });
         w.pce().bit(!matches!(config.parity, Parity::ParityNone));
         w