Add support for the RV32E variant #541
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Benchmarks
| Benchmark suite | Current: 64ea138 | Previous: d29f229 | Ratio |
|---|---|---|---|
Dhrystone |
1324 Average DMIPS over 10 runs |
1325 Average DMIPS over 10 runs |
1.00 |
Coremark |
969.943 Average iterations/sec over 10 runs |
964.643 Average iterations/sec over 10 runs |
0.99 |
This comment was automatically generated by workflow using github-action-benchmark.
eleanorLYJ
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Hi @ChinYikMing, In GitHub Actions, I encountered the following error during arch-tests:
It seems related to $PARALLEL in .ci/riscv-tests.sh. Do you have any ideas about this? Thanks! |
jserv
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Can you paste the link of the failed CI? |
Sure, Here's the link to the failed CI: https://github.com/sysprog21/rv32emu/actions/runs/12932773743/job/36080838856 |
It seems like segmentation fault is occurred. To pass the arch-test, |
Yes, this is indeed the issue. Thank you! |
FULL4G was a hack done by me. Let's completely get rid of such kludge. |
eleanorLYJ
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@eleanorLYJ Maybe adding the |
src/riscv.h
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| #define RV_REGS_LIST \ | ||
| _(zero) /* hard-wired zero, ignoring any writes */ \ | ||
| _(ra) /* return address */ \ | ||
| _(sp) /* stack pointer */ \ | ||
| _(gp) /* global pointer */ \ | ||
| _(tp) /* thread pointer */ \ | ||
| _(t0) /* temporary/alternate link register */ \ | ||
| _(t1) /* temporaries */ \ | ||
| _(t2) \ | ||
| _(s0) /* saved register/frame pointer */ \ | ||
| _(s1) \ | ||
| _(a0) /* function arguments / return values */ \ | ||
| _(a1) \ | ||
| _(a2) /* function arguments */ \ | ||
| _(a3) \ | ||
| _(a4) \ | ||
| _(a5) \ | ||
| IIF(RV32_HAS(RV32E)(, _(a6) _(a7) _(s2) /* saved register */ \ | ||
| _(s3) _(s4) _(s5) _(s6) _(s7) _(s8) _(s9) _(s10) \ | ||
| _(s11) _(t3) /* temporary register */ \ | ||
| _(t4) _(t5) _(t6))) |
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Rewrite as following:
/* clang-format off */
#define RV_REGS_LIST \
_(zero) /* hard-wired zero, ignoring any writes */ \
_(ra) /* return address */ \
_(sp) /* stack pointer */ \
_(gp) /* global pointer */ \
_(tp) /* thread pointer */ \
_(t0) /* temporary/alternate link register */ \
_(t1) /* temporaries */ \
_(t2) \
_(s0) /* saved register/frame pointer */ \
_(s1) \
_(a0) /* function arguments / return values */ \
_(a1) \
_(a2) /* function arguments */ \
_(a3) \
_(a4) \
_(a5) \
IIF(!RV32_HAS(RV32E)( \
_(a6) \
_(a7) \
_(s2) /* saved register */ \
_(s3) \
_(s4) \
_(s5) \
_(s6) \
_(s7) \
_(s8) \
_(s9) \
_(s10) \
_(s11) \
_(t3) /* temporary register */ \
_(t4) \
_(t5) \
_(t6) \
)
/* clang-format on */There was a problem hiding this comment.
If we use ! in IIF() macro, the following errors occur:
./src/common.h:216:30: error: pasting "IIF_" and "!" does not give a valid preprocessing token
216 | #define IIF(c) PRIMITIVE_CAT(IIF_, c)
| ^~~~
src/riscv.h:54:9: error: expected ‘,’ or ‘}’ before ‘!’ token
54 | IIF(!RV32_HAS(RV32E))( \
| ^
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If we use ! in IIF() macro, the following errors occurs:
Interesting! It means there is room to improve IIF macro.
Use the previous way for using IIF macro along with clang-format comments.
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I think there is a missing comma at the last line. i.e.
...
_(t5) \
_(t6) \
,)And the current IIF macro only accepts RV32_HAS(*) as its argument because it needs the expansion from IIF(RV32_HAS(*)) to IIF_0 or IIF_1.
eleanorLYJ
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The RV32E variant reduces the general-purpose registers to 16, optimizing the architecture for resource-constrained embedded microcontrollers. This addition enhances compatibility with the RISC-V specification and targets low-power, minimal-complexity systems.
Add RV32E to the list of supported features, customization options, and riscv-arch-test progress in the README.
Enable architecture tests for RV32E with appropriate handling of the reduced register set and ABI. With this change, users can run tests for RV32E using the following command: make arch-test RISCV_DEVICE=E
Add testing for the RV32E to the CI pipeline to ensure automatic validation during continuous integration.
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Thank @eleanorLYJ for contributing! |
Key changes:
The RV32E variant, which reduces the general-purpose registers to 16, is optimizing the architecture for resource-constrained embedded microcontrollers.
Impact:
This enhancement broadens the compatibility of the emulator with the RISC-V specification, specifically targeting low-power, minimal-complexity systems. The addition of CI tests ensures that the new functionality is robust and reliable.