Merge pull request #168 from DrXiao/refine-codegen

Refine code generation for address-of operations
sysprog21 · Nov 26, 2024 · 9bda64e · 9bda64e
2 parents a8bc7cf + 418d20e
commit 9bda64e
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Showing 2 changed files with 9 additions and 19 deletions.
diff --git a/src/arm-codegen.c b/src/arm-codegen.c
@@ -197,6 +197,7 @@ void emit_ph2_ir(ph2_ir_t *ph2_ir)
      * the instruction sequence of
      * 1. division and modulo.
      * 2. load and store operations.
+     * 3. address-of operations.
      */
     arm_reg interm;
 
@@ -219,20 +220,14 @@ void emit_ph2_ir(ph2_ir_t *ph2_ir)
             emit(__mov_i(__AL, rd, ph2_ir->src0));
         return;
     case OP_address_of:
-        if (ph2_ir->src0 > 255) {
-            emit(__movw(__AL, __r8, ph2_ir->src0));
-            emit(__movt(__AL, __r8, ph2_ir->src0));
-            emit(__add_r(__AL, rd, __sp, __r8));
-        } else
-            emit(__add_i(__AL, rd, __sp, ph2_ir->src0));
-        return;
     case OP_global_address_of:
+        interm = ph2_ir->op == OP_address_of ? __sp : __r12;
         if (ph2_ir->src0 > 255) {
             emit(__movw(__AL, __r8, ph2_ir->src0));
             emit(__movt(__AL, __r8, ph2_ir->src0));
-            emit(__add_r(__AL, rd, __r12, __r8));
+            emit(__add_r(__AL, rd, interm, __r8));
         } else
-            emit(__add_i(__AL, rd, __r12, ph2_ir->src0));
+            emit(__add_i(__AL, rd, interm, ph2_ir->src0));
         return;
     case OP_assign:
         emit(__mov_r(__AL, rd, rn));

diff --git a/src/riscv-codegen.c b/src/riscv-codegen.c
@@ -161,6 +161,7 @@ void emit_ph2_ir(ph2_ir_t *ph2_ir)
      * the instruction sequence of
      * 1. division and modulo.
      * 2. load and store operations.
+     * 3. address-of operations.
      */
     rv_reg interm, divisor_mask = __t1;
 
@@ -179,21 +180,15 @@ void emit_ph2_ir(ph2_ir_t *ph2_ir)
         } else
             emit(__addi(rd, __zero, ph2_ir->src0));
         return;
-    case OP_global_address_of:
-        if (ph2_ir->src0 < -2048 || ph2_ir->src0 > 2047) {
-            emit(__lui(__t0, rv_hi(ph2_ir->src0)));
-            emit(__addi(__t0, __t0, rv_lo(ph2_ir->src0)));
-            emit(__add(rd, __gp, __t0));
-        } else
-            emit(__addi(rd, __gp, ph2_ir->src0));
-        return;
     case OP_address_of:
+    case OP_global_address_of:
+        interm = ph2_ir->op == OP_address_of ? __sp : __gp;
         if (ph2_ir->src0 < -2048 || ph2_ir->src0 > 2047) {
             emit(__lui(__t0, rv_hi(ph2_ir->src0)));
             emit(__addi(__t0, __t0, rv_lo(ph2_ir->src0)));
-            emit(__add(rd, __sp, __t0));
+            emit(__add(rd, interm, __t0));
         } else
-            emit(__addi(rd, __sp, ph2_ir->src0));
+            emit(__addi(rd, interm, ph2_ir->src0));
         return;
     case OP_assign:
         emit(__addi(rd, rs1, 0));