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The RV64G Core is a 64-bit RISC-V compliant core designed in SystemVerilog. It includes the RV64IMAFD extensions, providing integer, multiplication/division, atomic, floating-point, and double-precision floating-point

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tahmeedKENJI/rv64g-core-experiment-tahmeed

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Introduction

The RV64G Core is a 64-bit RISC-V compliant core designed in SystemVerilog. It includes the RV64IMAFD extensions, providing integer, multiplication/division, atomic, floating-point, and double-precision floating-point

MaverickOne Architecture

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Directory Structure

  • .github: Repository Managements.
  • build: Auto generated. Contains builds of simulation.
  • document: Contains all files related to the documentation of the RTL.
  • include: Contains all headers, macros, constants, packages, etc., used in both RTL and TB.
  • log: Auto generated. Contains logs of simulation.
  • source: Contains the SystemVerilog RTL files.
  • submodules: Contains other git repositories as submodule to this repository.
  • test: Contains SystemVerilog testbench and it's relevant files.

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The RV64G Core is a 64-bit RISC-V compliant core designed in SystemVerilog. It includes the RV64IMAFD extensions, providing integer, multiplication/division, atomic, floating-point, and double-precision floating-point

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