Tweak BH csrrs init code

tenstorrent · Jan 13, 2025 · 30f0824 · 30f0824
1 parent 520c1dc
commit 30f0824
Showing 1 changed file with 2 additions and 8 deletions.
diff --git a/tt_metal/hw/inc/risc_common.h b/tt_metal/hw/inc/risc_common.h
@@ -183,22 +183,16 @@ inline __attribute__((always_inline)) void configure_l1_data_cache() {
     // L1 cache can be disabled by setting `TT_METAL_DISABLE_L1_DATA_CACHE_RISCVS` env var
     // export TT_METAL_DISABLE_L1_DATA_CACHE_RISCVS=<BR,NC,TR,ER>
     asm(R"ASM(
-        .option push
-        li   t1, 0x1
-        slli t1, t1, 3
+        li t1, 0x8
         csrrs zero, 0x7c0, t1
-        .option pop
          )ASM" ::
             : "t1");
 #elif !defined(ENABLE_HW_CACHE_INVALIDATION)
     // Disable gathering to stop HW from invalidating the data cache after 128 transactions
     // This is default enabled
     asm(R"ASM(
-        .option push
-        li   t1, 0x1
-        slli t1, t1, 18
+        lui  t1, 0x40
         csrrs zero, 0x7c0, t1
-        .option pop
          )ASM" ::
             : "t1");
 #endif