tianocore · nhivp · Nov 11, 2024 · Nov 9, 2024
@@ -0,0 +1,269 @@
+##
+# Mt. Jade Board Setting
+#
+# This is a collection of board and hardware configurations
+# for an Altra-based ARM64 platform. It is stored in the persistent storage.
+#
+##
+
+#
+# Name, offset (hex), value
+# value can be hex or decimal
+#
+
+NV_SI_RO_BOARD_VENDOR, 0x0000, 0x0000CD3A
+NV_SI_RO_BOARD_TYPE, 0x0008, 0x00000000
+NV_SI_RO_BOARD_REV, 0x0010, 0x00000000
+NV_SI_RO_BOARD_CFG, 0x0018, 0x00000000
+NV_SI_RO_BOARD_S0_DIMM_AVAIL, 0x0020, 0x0000FFFF
+NV_SI_RO_BOARD_S1_DIMM_AVAIL, 0x0028, 0x0000FFFF
+NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ, 0x0030, 0x000080E8
+NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ, 0x0038, 0x000080E8
+NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ, 0x0040, 0x00002710
+NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ, 0x0048, 0x00002710
+NV_SI_RO_BOARD_TPM_LOC, 0x0050, 0x00000000
+NV_SI_RO_BOARD_I2C0_FREQ_KHZ, 0x0058, 0x00000190
+NV_SI_RO_BOARD_I2C1_FREQ_KHZ, 0x0060, 0x00000190
+NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ, 0x0068, 0x00000190
+NV_SI_RO_BOARD_I2C3_FREQ_KHZ, 0x0070, 0x00000190
+NV_SI_RO_BOARD_I2C9_FREQ_KHZ, 0x0078, 0x00000190
+NV_SI_RO_BOARD_2P_CFG, 0x0080, 0xFFFFFF01
+NV_SI_RO_BOARD_S0_RCA0_CFG, 0x0088, 0x00000000
+NV_SI_RO_BOARD_S0_RCA1_CFG, 0x0090, 0x00000000
+NV_SI_RO_BOARD_S0_RCA2_CFG, 0x0098, 0x00000004
+NV_SI_RO_BOARD_S0_RCA3_CFG, 0x00A0, 0x00000004
+NV_SI_RO_BOARD_S0_RCB0_LO_CFG, 0x00A8, 0x00020002
+NV_SI_RO_BOARD_S0_RCB0_HI_CFG, 0x00B0, 0x00020002
+NV_SI_RO_BOARD_S0_RCB1_LO_CFG, 0x00B8, 0x00020002
+NV_SI_RO_BOARD_S0_RCB1_HI_CFG, 0x00C0, 0x00020002
+NV_SI_RO_BOARD_S0_RCB2_LO_CFG, 0x00C8, 0x00020002
+NV_SI_RO_BOARD_S0_RCB2_HI_CFG, 0x00D0, 0x00000003
+NV_SI_RO_BOARD_S0_RCB3_LO_CFG, 0x00D8, 0x00000003
+NV_SI_RO_BOARD_S0_RCB3_HI_CFG, 0x00E0, 0x00020002
+NV_SI_RO_BOARD_S1_RCA0_CFG, 0x00E8, 0x00000000
+NV_SI_RO_BOARD_S1_RCA1_CFG, 0x00F0, 0x00000000
+NV_SI_RO_BOARD_S1_RCA2_CFG, 0x00F8, 0x02020202
+NV_SI_RO_BOARD_S1_RCA3_CFG, 0x0100, 0x00030003
+NV_SI_RO_BOARD_S1_RCB0_LO_CFG, 0x0108, 0x00000003
+NV_SI_RO_BOARD_S1_RCB0_HI_CFG, 0x0110, 0x00020002
+NV_SI_RO_BOARD_S1_RCB1_LO_CFG, 0x0118, 0x00020002
+NV_SI_RO_BOARD_S1_RCB1_HI_CFG, 0x0120, 0x00000003
+NV_SI_RO_BOARD_S1_RCB2_LO_CFG, 0x0128, 0x00020002
+NV_SI_RO_BOARD_S1_RCB2_HI_CFG, 0x0130, 0x00020002
+NV_SI_RO_BOARD_S1_RCB3_LO_CFG, 0x0138, 0x00020002
+NV_SI_RO_BOARD_S1_RCB3_HI_CFG, 0x0140, 0x00020002
+NV_SI_RO_BOARD_T_LTLM_DELTA_P0, 0x0148, 0x00000001
+NV_SI_RO_BOARD_T_LTLM_DELTA_P1, 0x0150, 0x00000002
+NV_SI_RO_BOARD_T_LTLM_DELTA_P2, 0x0158, 0x00000003
+NV_SI_RO_BOARD_T_LTLM_DELTA_P3, 0x0160, 0x00000004
+NV_SI_RO_BOARD_T_LTLM_DELTA_M1, 0x0168, 0xFFFFFFFF
+NV_SI_RO_BOARD_T_LTLM_DELTA_M2, 0x0170, 0xFFFFFFFE
+NV_SI_RO_BOARD_T_LTLM_DELTA_M3, 0x0178, 0xFFFFFFFD
+NV_SI_RO_BOARD_P_LM_PID_P, 0x0180, 0x00000000
+NV_SI_RO_BOARD_P_LM_PID_I, 0x0188, 0x00000000
+NV_SI_RO_BOARD_P_LM_PID_I_L_THOLD, 0x0190, 0x00000000
+NV_SI_RO_BOARD_P_LM_PID_I_H_THOLD, 0x0198, 0x00000000
+NV_SI_RO_BOARD_P_LM_PID_D, 0x01A0, 0x00000000
+NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST, 0x01A8, 0x00000000
+NV_SI_RO_BOARD_TPM_ALG_ID, 0x01B0, 0x00000002
+NV_SI_RO_BOARD_DDR_SPEED_GRADE, 0x01B8, 0x00000C80
+NV_SI_RO_BOARD_DDR_S0_RTT_WR, 0x01C0, 0x20020000
+NV_SI_RO_BOARD_DDR_S1_RTT_WR, 0x01C8, 0x20020000
+NV_SI_RO_BOARD_DDR_S0_RTT_NOM, 0x01D0, 0x31060177
+NV_SI_RO_BOARD_DDR_S1_RTT_NOM, 0x01D8, 0x31060177
+NV_SI_RO_BOARD_DDR_S0_RTT_PARK, 0x01E0, 0x30060070
+NV_SI_RO_BOARD_DDR_S1_RTT_PARK, 0x01E8, 0x30060070
+NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_1DPC, 0x01F0, 0x00000000
+NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_1DPC, 0x01F8, 0x00000000
+NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_1DPC, 0x0200, 0x00000000
+NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_1DPC, 0x0208, 0x00000000
+NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_2DPC, 0x0210, 0x044C0CCC
+NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_2DPC, 0x0218, 0x084C0CCC
+NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_2DPC, 0x0220, 0x04130333
+NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_2DPC, 0x0228, 0x08130333
+NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_1DPC, 0x0230, 0x01130333
+NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_1DPC, 0x0238, 0x02230333
+NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_1DPC, 0x0240, 0x01430333
+NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_1DPC, 0x0248, 0x02830333
+NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_2DPC, 0x0250, 0x055EDEED
+NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_2DPC, 0x0258, 0x0A5DEDDE
+NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_2DPC, 0x0260, 0x055B7BB7
+NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_2DPC, 0x0268, 0x0A57B77B
+NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_1DPC, 0x0270, 0x00000005
+NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_1DPC, 0x0278, 0x0090DD90
+NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_1DPC, 0x0280, 0x00000005
+NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_1DPC, 0x0288, 0x0090DD90
+NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_2DPC, 0x0290, 0x00000005
+NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_2DPC, 0x0298, 0x0090DD90
+NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_2DPC, 0x02A0, 0x00000005
+NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_2DPC, 0x02A8, 0x0090DD90
+NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_1DPC, 0x02B0, 0x00000024
+NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_1DPC, 0x02B8, 0x001A001A
+NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_2DPC, 0x02C0, 0x00000050
+NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_2DPC, 0x02C8, 0x00240020
+NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_DEFAULT, 0x02D0, 0x02800280
+NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_DEFAULT, 0x02D8, 0x90909090
+NV_SI_RO_BOARD_DDR_WRDQS_SHIFT_DEFAULT, 0x02E0, 0x00000000
+NV_SI_RO_BOARD_DDR_ADCMD_DLY_DEFAULT, 0x02E8, 0x00C000C0
+NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_ADJ, 0x02F0, 0x00000000
+NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_ADJ, 0x02F8, 0x00000000
+NV_SI_RO_BOARD_DDR_PHY_VREF_ADJ, 0x0300, 0x00000000
+NV_SI_RO_BOARD_DDR_DRAM_VREF_ADJ, 0x0308, 0x00000000
+NV_SI_RO_BOARD_DDR_WR_PREAMBLE_CYCLE, 0x0310, 0x02010201
+NV_SI_RO_BOARD_DDR_ADCMD_2T_MODE, 0x0318, 0x00000000
+NV_SI_RO_BOARD_I2C_VRD_CONFIG_INFO, 0x0320, 0x00000000
+NV_SI_RO_BOARD_DDR_PHY_FEATURE_CTRL, 0x0328, 0x00000000
+NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_ACCESS, 0x0330, 0x01050106
+NV_SI_RO_BOARD_DIMM_TEMP_THRESHOLD, 0x0338, 0x000005F4
+NV_SI_RO_BOARD_DIMM_SPD_COMPARE_DISABLE, 0x0340, 0x00000000
+NV_SI_RO_BOARD_S0_PCIE_CLK_CFG, 0x0348, 0x00000000
+NV_SI_RO_BOARD_S0_RCA4_CFG, 0x0350, 0x02020202
+NV_SI_RO_BOARD_S0_RCA5_CFG, 0x0358, 0x02020202
+NV_SI_RO_BOARD_S0_RCA6_CFG, 0x0360, 0x02020202
+NV_SI_RO_BOARD_S0_RCA7_CFG, 0x0368, 0x00030003
+NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET, 0x0370, 0xFFFFFFFF
+NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET, 0x0378, 0xFFFFFFFF
+NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET, 0x0380, 0xFFFFFFFF
+NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET, 0x0388, 0xFFFFFFFF
+NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET, 0x0390, 0x00000000
+NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET, 0x0398, 0x00000000
+NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET, 0x03A0, 0x00000000
+NV_SI_RO_BOARD_S0_RCB1B_TXRX_G3PRESET, 0x03A8, 0x00000000
+NV_SI_RO_BOARD_S0_RCB2A_TXRX_G3PRESET, 0x03B0, 0x00000000
+NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET, 0x03B8, 0x00000000
+NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET, 0x03C0, 0x00000000
+NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET, 0x03C8, 0x00000000
+NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET, 0x03D0, 0xFFFFFFFF
+NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET, 0x03D8, 0xFFFFFFFF
+NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET, 0x03E0, 0xFFFFFFFF
+NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET, 0x03E8, 0xFFFFFFFF
+NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET, 0x03F0, 0x57575757
+NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET, 0x03F8, 0x57575757
+NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET, 0x0400, 0x57575757
+NV_SI_RO_BOARD_S0_RCA3_TXRX_G4PRESET, 0x0408, 0x57575757
+NV_SI_RO_BOARD_S0_RCB0A_TXRX_G4PRESET, 0x0410, 0x57575757
+NV_SI_RO_BOARD_S0_RCB0B_TXRX_G4PRESET, 0x0418, 0x57575757
+NV_SI_RO_BOARD_S0_RCB1A_TXRX_G4PRESET, 0x0420, 0x57575757
+NV_SI_RO_BOARD_S0_RCB1B_TXRX_G4PRESET, 0x0428, 0x57575757
+NV_SI_RO_BOARD_S0_RCB2A_TXRX_G4PRESET, 0x0430, 0x57575757
+NV_SI_RO_BOARD_S0_RCB2B_TXRX_G4PRESET, 0x0438, 0x57575757
+NV_SI_RO_BOARD_S0_RCB3A_TXRX_G4PRESET, 0x0440, 0x57575757
+NV_SI_RO_BOARD_S0_RCB3B_TXRX_G4PRESET, 0x0448, 0x57575757
+NV_SI_RO_BOARD_S0_RCA4_TXRX_G4PRESET, 0x0450, 0x57575757
+NV_SI_RO_BOARD_S0_RCA5_TXRX_G4PRESET, 0x0458, 0x57575757
+NV_SI_RO_BOARD_S0_RCA6_TXRX_G4PRESET, 0x0460, 0x57575757
+NV_SI_RO_BOARD_S0_RCA7_TXRX_G4PRESET, 0x0468, 0x57575757
+NV_SI_RO_BOARD_S1_PCIE_CLK_CFG, 0x0470, 0x00000000
+NV_SI_RO_BOARD_S1_RCA4_CFG, 0x0478, 0x00030003
+NV_SI_RO_BOARD_S1_RCA5_CFG, 0x0480, 0x02020202
+NV_SI_RO_BOARD_S1_RCA6_CFG, 0x0488, 0x02020202
+NV_SI_RO_BOARD_S1_RCA7_CFG, 0x0490, 0x02020202
+NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET, 0x0498, 0xFFFFFFFF
+NV_SI_RO_BOARD_S1_RCA3_TXRX_G3PRESET, 0x04A0, 0xFFFFFFFF
+NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET, 0x04A8, 0x00000000
+NV_SI_RO_BOARD_S1_RCB0B_TXRX_G3PRESET, 0x04B0, 0x00000000
+NV_SI_RO_BOARD_S1_RCB1A_TXRX_G3PRESET, 0x04B8, 0x00000000
+NV_SI_RO_BOARD_S1_RCB1B_TXRX_G3PRESET, 0x04C0, 0x00000000
+NV_SI_RO_BOARD_S1_RCB2A_TXRX_G3PRESET, 0x04C8, 0x00000000
+NV_SI_RO_BOARD_S1_RCB2B_TXRX_G3PRESET, 0x04D0, 0x00000000
+NV_SI_RO_BOARD_S1_RCB3A_TXRX_G3PRESET, 0x04D8, 0x00000000
+NV_SI_RO_BOARD_S1_RCB3B_TXRX_G3PRESET, 0x04E0, 0x00000000
+NV_SI_RO_BOARD_S1_RCA4_TXRX_G3PRESET, 0x04E8, 0xFFFFFFFF
+NV_SI_RO_BOARD_S1_RCA5_TXRX_G3PRESET, 0x04F0, 0xFFFFFFFF
+NV_SI_RO_BOARD_S1_RCA6_TXRX_G3PRESET, 0x04F8, 0xFFFFFFFF
+NV_SI_RO_BOARD_S1_RCA7_TXRX_G3PRESET, 0x0500, 0xFFFFFFFF
+NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET, 0x0508, 0x57575757
+NV_SI_RO_BOARD_S1_RCA3_TXRX_G4PRESET, 0x0510, 0x57575757
+NV_SI_RO_BOARD_S1_RCB0A_TXRX_G4PRESET, 0x0518, 0x57575757
+NV_SI_RO_BOARD_S1_RCB0B_TXRX_G4PRESET, 0x0520, 0x57575757
+NV_SI_RO_BOARD_S1_RCB1A_TXRX_G4PRESET, 0x0528, 0x57575757
+NV_SI_RO_BOARD_S1_RCB1B_TXRX_G4PRESET, 0x0530, 0x57575757
+NV_SI_RO_BOARD_S1_RCB2A_TXRX_G4PRESET, 0x0538, 0x57575757
+NV_SI_RO_BOARD_S1_RCB2B_TXRX_G4PRESET, 0x0540, 0x57575757
+NV_SI_RO_BOARD_S1_RCB3A_TXRX_G4PRESET, 0x0548, 0x57575757
+NV_SI_RO_BOARD_S1_RCB3B_TXRX_G4PRESET, 0x0550, 0x57575757
+NV_SI_RO_BOARD_S1_RCA4_TXRX_G4PRESET, 0x0558, 0x57575757
+NV_SI_RO_BOARD_S1_RCA5_TXRX_G4PRESET, 0x0560, 0x57575757
+NV_SI_RO_BOARD_S1_RCA6_TXRX_G4PRESET, 0x0568, 0x57575757
+NV_SI_RO_BOARD_S1_RCA7_TXRX_G4PRESET, 0x0570, 0x57575757
+NV_SI_RO_BOARD_2P_CE_MASK_THRESHOLD, 0x0578, 0x00000003
+NV_SI_RO_BOARD_2P_CE_MASK_INTERVAL, 0x0580, 0x000001A4
+NV_SI_RO_BOARD_SX_PHY_CFG_SETTING, 0x0588, 0x00000000
+NV_SI_RO_BOARD_DDR_PHY_DC_CLK, 0x0590, 0x00018000
+NV_SI_RO_BOARD_DDR_PHY_DC_DATA, 0x0598, 0x80018000
+NV_SI_RO_BOARD_SX_RCA0_TXRX_20GPRESET, 0x05A0, 0x00000000
+NV_SI_RO_BOARD_SX_RCA1_TXRX_20GPRESET, 0x05A8, 0x00000000
+NV_SI_RO_BOARD_SX_RCA2_TXRX_20GPRESET, 0x05B0, 0x00000000
+NV_SI_RO_BOARD_SX_RCA3_TXRX_20GPRESET, 0x05B8, 0x00000000
+NV_SI_RO_BOARD_SX_RCA0_TXRX_25GPRESET, 0x05C0, 0x00000000
+NV_SI_RO_BOARD_SX_RCA1_TXRX_25GPRESET, 0x05C8, 0x00000000
+NV_SI_RO_BOARD_SX_RCA2_TXRX_25GPRESET, 0x05D0, 0x00000000
+NV_SI_RO_BOARD_SX_RCA3_TXRX_25GPRESET, 0x05D8, 0x00000000
+NV_SI_RO_BOARD_DDR_2X_REFRESH_TEMP_THRESHOLD, 0x05E0, 0x00550055
+NV_SI_RO_BOARD_PCP_VRD_VOUT_WAIT_US, 0x05E8, 0x00000064
+NV_SI_RO_BOARD_PCP_VRD_VOUT_RESOLUTION_MV, 0x05F0, 0x00000005
+NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_EN, 0x05F8, 0x00000001
+NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_TIME, 0x0600, 0x00000002
+NV_SI_RO_BOARD_DVFS_VOUT_20MV_RAMP_TIME_US, 0x0608, 0x00000005
+NV_SI_RO_BOARD_PCIE_AER_FW_FIRST, 0x0610, 0x00000000
+NV_SI_RO_BOARD_RTC_GPI_LOCK_BYPASS, 0x0618, 0x00000000
+NV_SI_RO_BOARD_TPM_DISABLE, 0x0620, 0x00000000
+NV_SI_RO_BOARD_MESH_S0_CXG_RC_STRONG_ORDERING_EN, 0x0628, 0x00000000
+NV_SI_RO_BOARD_MESH_S1_CXG_RC_STRONG_ORDERING_EN, 0x0630, 0x00000000
+NV_SI_RO_BOARD_GPIO_SW_WATCHDOG_EN, 0x0638, 0x00000000
+NV_SI_RO_BOARD_PCIE_HP_DISABLE, 0x0640, 0x00000000
+NV_SI_RO_BOARD_I2C_VRD_VOUT_FORMAT, 0x0648, 0x00000000
+NV_SI_RO_BOARD_I2C_VRD_SMBUS_CMD_FLAGS, 0x0650, 0x00000000
+NV_SI_RO_BOARD_CUST_SPM_LOCATION, 0x0658, 0x00000000
+NV_SI_RO_BOARD_RAS_DDR_CE_WINDOW, 0x0660, 0x00000000
+NV_SI_RO_BOARD_RAS_DDR_CE_TH1, 0x0668, 0x000001F4
+NV_SI_RO_BOARD_RAS_DDR_CE_TH2, 0x0670, 0x00001388
+NV_SI_RO_BOARD_RAS_DDR_CE_THC, 0x0678, 0x00000000
+NV_SI_RO_BOARD_MQ_SX_RCA0_TXRX_20GPRESET, 0x0680, 0x00000000
+NV_SI_RO_BOARD_MQ_SX_RCA1_TXRX_20GPRESET, 0x0688, 0x00000000
+NV_SI_RO_BOARD_MQ_SX_RCA0_TXRX_25GPRESET, 0x0690, 0x00000000
+NV_SI_RO_BOARD_MQ_SX_RCA1_TXRX_25GPRESET, 0x0698, 0x00000000
+NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G3PRESET, 0x06A0, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S0_RCA1_TXRX_G3PRESET, 0x06A8, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S0_RCA2_TXRX_G3PRESET, 0x06B0, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S0_RCA3_TXRX_G3PRESET, 0x06B8, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S0_RCA4_TXRX_G3PRESET, 0x06C0, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S0_RCA5_TXRX_G3PRESET, 0x06C8, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S0_RCA6_TXRX_G3PRESET, 0x06D0, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S0_RCA7_TXRX_G3PRESET, 0x06D8, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G3PRESET, 0x06E0, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S1_RCA3_TXRX_G3PRESET, 0x06E8, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S1_RCA4_TXRX_G3PRESET, 0x06F0, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S1_RCA5_TXRX_G3PRESET, 0x06F8, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S1_RCA6_TXRX_G3PRESET, 0x0700, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S1_RCA7_TXRX_G3PRESET, 0x0708, 0xFFFFFFFF
+NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G4PRESET, 0x0710, 0x57575757
+NV_SI_RO_BOARD_MQ_S0_RCA1_TXRX_G4PRESET, 0x0718, 0x57575757
+NV_SI_RO_BOARD_MQ_S0_RCA2_TXRX_G4PRESET, 0x0720, 0x57575757
+NV_SI_RO_BOARD_MQ_S0_RCA3_TXRX_G4PRESET, 0x0728, 0x57575757
+NV_SI_RO_BOARD_MQ_S0_RCA4_TXRX_G4PRESET, 0x0730, 0x57575757
+NV_SI_RO_BOARD_MQ_S0_RCA5_TXRX_G4PRESET, 0x0738, 0x57575757
+NV_SI_RO_BOARD_MQ_S0_RCA6_TXRX_G4PRESET, 0x0740, 0x57575757
+NV_SI_RO_BOARD_MQ_S0_RCA7_TXRX_G4PRESET, 0x0748, 0x57575757
+NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G4PRESET, 0x0750, 0x57575757
+NV_SI_RO_BOARD_MQ_S1_RCA3_TXRX_G4PRESET, 0x0758, 0x57575757
+NV_SI_RO_BOARD_MQ_S1_RCA4_TXRX_G4PRESET, 0x0760, 0x57575757
+NV_SI_RO_BOARD_MQ_S1_RCA5_TXRX_G4PRESET, 0x0768, 0x57575757
+NV_SI_RO_BOARD_MQ_S1_RCA6_TXRX_G4PRESET, 0x0770, 0x57575757
+NV_SI_RO_BOARD_MQ_S1_RCA7_TXRX_G4PRESET, 0x0778, 0x57575757
+NV_SI_RO_BOARD_RAS_FLAGS, 0x0780, 0x00000000
+NV_SI_RO_BOARD_DDR_PROGRESS_LOG_CTRL, 0x0788, 0x00000000
+NV_SI_RO_BOARD_2P_ALI_CE_MASK_THRESHOLD, 0x0790, 0x00000001
+NV_SI_RO_BOARD_2P_ALI_CE_MASK_INTERVAL, 0x0798, 0x00000000
+NV_SI_RO_BOARD_RAS_2P_CE_FILTER, 0x07A0, 0x00000000
+NV_SI_RO_BOARD_PCIE_AER_CE_THRESHOLD_EN, 0x07A8, 0x00000000
+NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_TO1, 0x07B0, 0x00000000
+NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_TO2, 0x07B8, 0x00000000
+NV_SI_RO_BOARD_PCIE_AER_CE_THRESHOLD, 0x07C0, 0x00000001
+NV_SI_RO_BOARD_PCIE_AER_CE_INTERVAL, 0x07C8, 0x00000000
+NV_SI_RO_BOARD_I2C_RCA_VRD_VOUT_FORMAT, 0x07D0, 0x00000000
+NV_SI_RO_BOARD_CCIX_MODE_OVERWRITE, 0x07D8, 0x00000000
+NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_MARGIN_MV, 0x07E0, 0x00000000
+NV_SI_RO_BOARD_2P_DPLL, 0x07E8, 0x00000000
+NV_SI_RO_BOARD_RC_DOMAIN_CTRL, 0x07F0, 0x00000000
+NV_SI_RO_BOARD_PCIE_SRIS_MODE, 0x07F8, 0x00000000