Trace-driven cache memory simulator with LRU, MRU, RR and Belady replacement policies.

"vcache" is a library that provides a concurrent-safe in-memory cache to store key-value pairs.

Exerting coherency between caches with protocols in a Memory-Shared Multiprocessors system whether it has uniform memory access(UMA, symmetric) or not(non-UMA).

This project is an implementation of cache memory with load and store instructions in Verilog.

Um programa que simula o referenciamento do endereço da memória principal na memória cache.

ASP.NET Core (.NET 6) Web API + cache (Redis, Memory)

A simulator of cache system behavior.

Cache memory management project. Technologies and languages used: C++. University. Computer Structure.

Small, lightweight GRPC cache memory service for use in distributed or separate systems with the ability to separate information from each system

Codigo python para simular lecturas de un sistema de memoria con RAM y Caché

Solution to cachelab of CMU-213

https://youtu.be/yMGAbm84iIY

Esse projeto explora a configuração de cache em aplicações Spring Boot.

Logisim implementation of computer architecture lab assignment and other necessary items

Computer forensic using autospy, wireshark, etc.

Created a Url shortening service like Bitly & tinyurl for easy sharing of long urls, also implemented caching to deliver quick responses.

design of cache memory in computer architeture

Hands-on exercise for DPE University

ARM processor implementation, hazard unit, forwarding unit, SRAM & cache memory.