v0.3.0 release

Evolution summary:

core

new

• main: add optional probe-firmware
• main: add option to specify device index
• part: add irlength and introduce new structure for device not handled (CPU) mainly for irlength
• jtag: add logic to handle multiple device in JTAG chain

update

• spiFlash: introduce jedec_id
• main: rework fpga detection to allows more than one device in a chain, but only FPGA is allowed

fix

• spiFlash: add a workaround for microchip SST26VF032B / SST26VF032BA
• main: fix default args.index_chain

cable

new

• Digilent Digital Discovery and Analog Discovery 2
• cmsis dap (hid) support
• cypress fx2 low level
• DFU protocol support
• usb-blasterII

update

• usbBlaster: add a low level to support both usbBlasterI(ftdi) and usbBlasterII(fx2)
• dirtyJtag: optimizations to cut the number of USB requests

fix

• allow 232H devices to have upper bank pins configured on init.

boards

new

• Alchitry Au
• basys3
• colorlight I5
• digilent zedboard
• minispartan6
• orangeCrab
• terasic de0nanoSoc
• terasic de10nano

parts

new

• intel cycloneV Soc 5CSEMA4, 5CSEBA6
• lattice MachXO2 LCMXO2-1200HC
• xilinx artix 7 75t
• xilinx spartan6 xc6slx9, xc6slx16, xc6slx25
• xilinx zynq 7020

update

• lattice: move directly to run_test_idle with last tx packet
• rework xilinx fpga spiOverJtag to respect model/package
• altera: adapt delay according to clock freq

fix

• xilinx: be more verbose when spiOverJtag not available
• xilinx: supress useless test in spi_wait

bitstream/file type

new

• ihexParser

fix

• fsparser: fix checksum with GW1NS-2C, when configuration data is smaller than theory
• fsparser: don't try to analyze header after then end of header area
• fsparser: drop CR at the end of line
• configBitstreamParser: fix CRLF vs LF: use fread with FILE (or stdin) instead of c++ stream

Contributors:

• GEORGIOS KARNAS (@kargeor)
• phdussud (@phdussud)
• ultraembedded (@ultraembedded)