My solutions to problem sets on HDLBits (https://hdlbits.01xz.net).
Usage:
node index.js
- Getting Started (Solution: step_one.v)
- Output Zero (Solution: zero.v)
- Simple wire (Solution: wire.v)
- Four wires (Solution: wire4.v)
- Inverter (Solution: notgate.v)
- AND gate (Solution: andgate.v)
- NOR gate (Solution: norgate.v)
- XNOR gate (Solution: xnorgate.v)
- Declaring wires (Solution: wire_decl.v)
- 7458 chip (Solution: 7458.v)
- Vectors (Solution: vector0.v)
- Vectors in more detail (Solution: vector1.v)
- Vector part select (Solution: vector2.v)
- Bitwise operators (Solution: vectorgates.v)
- Four-input gates (Solution: gates4.v)
- Vector concatenation operator (Solution: vector3.v)
- Vector reversal 1 (Solution: vectorr.v)
- Replication operator (Solution: vector4.v)
- More replication (Solution: vector5.v)
- Modules (Solution: module.v)
- Connecting ports by position (Solution: module_pos.v)
- Connecting ports by name (Solution: module_name.v)
- Three modules (Solution: module_shift.v)
- Modules and vectors (Solution: module_shift8.v)
- Adder 1 (Solution: module_add.v)
- Adder 2 (Solution: module_fadd.v)
- Carry-select adder (Solution: module_cseladd.v)
- Adder-subtractor (Solution: module_addsub.v)
- Always blocks (combinational) (Solution: alwaysblock1.v)
- Always blocks (clocked) (Solution: alwaysblock2.v)
- If statement (Solution: always_if.v)
- If statement latches (Solution: always_if2.v)
- Case statement (Solution: always_case.v)
- Priority encoder (Solution: always_case2.v)
- Priority encoder with casez (Solution: always_casez.v)
- Avoiding latches (Solution: always_nolatches.v)
- Conditional ternary operator (Solution: conditional.v)
- Reduction operators (Solution: reduction.v)
- Reduction: Even wider gates (Solution: gates100.v)
- Combinational for-loop: Vector reversal 2 (Solution: vector100r.v)
- Combinational for-loop: 255-bit population count (Solution: popcount255.v)
- Generate for-loop: 100-bit binary adder 2 (Solution: adder100i.v)
- Generate for-loop: 100-digit BCD adder (Solution: bcdadd100.v)
- Wire (Solution: m2014_q4h.v)
- GND (Solution: m2014_q4i.v)
- NOR (Solution: m2014_q4e.v)
- Another gate (Solution: m2014_q4f.v)
- Two gates (Solution: m2014_q4g.v)
- More logic gates (Solution: gates.v)
- 7420 chip (Solution: 7420.v)
- Truth tables (Solution: truthtable1.v)
- Two-bit equality (Solution: mt2015_eq2.v)
- Simple circuit A (Solution: mt2015_q4a.v)
- Simple circuit B (Solution: mt2015_q4b.v)
- Combine circuits A and B (Solution: mt2015_q4.v)
- Ring or vibrate? (Solution: ringer.v)
- Thermostat (Solution: thermostat.v)
- 3-bit population count (Solution: popcount3.v)
- Gates and vectors (Solution: gatesv.v)
- Even longer vectors (Solution: gatesv100.v)
- 2-to-1 multiplexer (Solution: mux2to1.v)
- 2-to-1 bus multiplexer (Solution: mux2to1v.v)
- 9-to-1 multiplexer (Solution: mux9to1v.v)
- 256-to-1 multiplexer (Solution: mux256to1.v)
- 256-to-1 4-bit multiplexer (Solution: mux256to1v.v)
- Half adder (Solution: hadd.v)
- Full adder (Solution: fadd.v)
- 3-bit binary adder (Solution: adder3.v)
- Adder (Solution: m2014_q4j.v)
- Signed addition overflow (Solution: ece241_2014_q1c.v)
- 100-bit binary adder (Solution: adder100.v)
- 4-digit BCD adder
- 3-variable
- 4-variable
- 4-variable
- 4-variable
- Minimum SOP and POS
- Karnaugh map
- Karnaugh map
- K-map implemented with a multiplexer
- D flip-flop (Solution: dff.v)
- D flip-flops (Solution: dff8.v)
- DFF with reset (Solution: dff8r.v)
- DFF with reset value (Solution: dff8p.v)
- DFF with asynchronous reset (Solution: dff8ar.v)
- DFF with byte enable (Solution: dff16e.v)
- D Latch (Solution: m2014_q4a.v)
- DFF (Solution: m2014_q4b.v)
- DFF (Solution: m2014_q4c.v)
- DFF+gate (Solution: m2014_q4d.v)
- Mux and DFF (Solution: mt2015_muxdff.v)
- Mux and DFF (Solution: 2014_q4a.v)
- DFFs and gates (Solution: ece241_2014_q4.v)
- Create circuit from truth table (Solution: ece241_2013_q7.v)
- Detect an edge (Solution: edgedetect.v)
- Detect both edges (Solution: edgedetect2.v)
- Edge capture register (Solution: edgecapture.v)
- Dual-edge triggered flip-flop (Solution: dualedge.v)
- Four-bit binary counter (Solution: count15.v)
- Decade counter (Solution: count10.v)
- Decade counter again (Solution: count1to10.v)
- Slow decade counter (Solution: countslow.v)
- Counter 1-12 (Solution: ece241_2014_q7a.v)
- Counter 1000
- 4-digit decimal counter
- 12-hour clock
- 4-bit shift register (Solution: shift4.v)
- Left/right rotator
- Left/right arithmetic shift by 1 or 8
- 5-bit LFSR
- 3-bit LFSR
- 32-bit LFSR
- Shift register
- Shift register
- 3-input LUT
- Simple FSM 1 (asynchronous reset) (Solution: fsm1.v)
- Simple FSM 1 (synchronous reset) (Solution: fsm1s.v)
- Simple FSM 2 (asynchronous reset)
- Simple FSM 2 (synchronous reset)
- Simple state transitions 3
- Simple one-hot state transitions 3
- Simple FSM 3 (asynchronous reset)
- Simple FSM 3 (synchronous reset)
- Design a Moore FSM
- Lemmings 1
- Lemmings 2
- Lemmings 3
- Lemmings 4
- One-hot FSM
- PS/2 packet parser
- PS/2 packet parser and datapath
- Serial receiver
- Serial receiver and datapath
- Serial receiver with parity checking
- Sequence recognition
- Q8: Design a Mealy FSM
- Q5a: Serial two's complementer (Moore FSM)
- Q5b: Serial two's complementer (Mealy FSM)
- Q3a: FSM
- Q3b: FSM
- Q3c: FSM logic
- Q6b: FSM next-state logic
- Q6c: FSM one-hot next-state logic
- Q6: FSM
- Q2a: FSM
- Q2b: One-hot FSM equations
- Q2a: FSM
- Q2b: Another FSM
- Counter with period 1000
- 4-bit shift register and down counter
- FSM: Sequence 1101 recognizer
- FSM: Enable shift register
- FSM: The complete FSM
- The complete timer
- FSM: One-hot logic equations