Specify different switch type to drive wires with different directions

libs/libarchfpga/src/physical_types.h

@@ -1561,6 +1561,12 @@ enum e_Fc_type {
  *                   relation to the switches from the architecture file,    *
  *                   not the expanded list of switches that is built         *
  *                   at the end of build_rr_graph                            *
+ * @param arch_wire_switch_dec: Same as arch_wire_switch but used only for   *
+ *                   decremental tracks if it is specified in the            *
+ *                   architecture file.                                      *
+ * @param arch_opin_switch_dec: Same as arch_opin_switch but used only for   *
+ *                   decremental tracks if it is specified in the            *
+ *                   architecture file                                       * 
  *                                                                           *
  * @param arch_opin_between_dice_switch: Index of the switch type that       *
  *                   connects output pins (OPINs) *to* this segment from     *
@@ -1579,14 +1585,14 @@ enum e_Fc_type {
  * Cmetal: Capacitance of a routing track, per unit logic block length.      *
  * Rmetal: Resistance of a routing track, per unit logic block length.       *
  * (UDSD by AY) drivers: How do signals driving a routing track connect to   *
- *                       the track?  
+ *                       the track?                                          *
  * seg_index: The index of the segment as stored in the appropriate Segs list*
  *            Upon loading the architecture, we use this field to keep track *
  *            the segment's index in the unified segment_inf vector. This is *
  *            useful when building the rr_graph for different Y & X channels *
- *            in terms of track distribution and segment type.                *
+ *            in terms of track distribution and segment type.               *
  * res_type: Determines the routing network to which the segment belongs.    *
- *           Possible values are:
+ *           Possible values are:                                            *
  *              - GENERAL: The segment is part of the general routing        *
  *                         resources.                                        *
  *              - GCLK: The segment is part of the global routing network.   *
@@ -1600,6 +1606,8 @@ struct t_segment_inf {
     int length;
     short arch_wire_switch;
     short arch_opin_switch;
+    short arch_wire_switch_dec;
+    short arch_opin_switch_dec;
     short arch_opin_between_dice_switch = -1;
     float frac_cb;
     float frac_sb;

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -3766,6 +3766,10 @@ static void ProcessSegments(pugi::xml_node Parent,
             //Unidir requires the following tags
             expected_subtags.emplace_back("mux");
             expected_subtags.emplace_back("mux_inter_die");
+            //with the following two tags, we can allow the architecture file to define
+            //different muxes with different delays for wires with different directions
+            expected_subtags.emplace_back("mux_inc");
+            expected_subtags.emplace_back("mux_dec");
         }
 
         else {
@@ -3796,28 +3800,78 @@ static void ProcessSegments(pugi::xml_node Parent,
         /* Get the wire and opin switches, or mux switch if unidir */
         if (UNI_DIRECTIONAL == Segs[i].directionality) {
             //Get the switch name for same die wire and track connections
-            SubElem = get_single_child(Node, "mux", loc_data);
-            tmp = get_attribute(SubElem, "name", loc_data).value();
-
-            /* Match names */
-            for (j = 0; j < NumSwitches; ++j) {
-                if (0 == strcmp(tmp, Switches[j].name.c_str())) {
-                    break; /* End loop so j is where we want it */
+            SubElem = get_single_child(Node, "mux", loc_data, ReqOpt::OPTIONAL);
+            tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
+
+            //check if <mux> tag is defined in the architecture, otherwise we should look for <mux_inc> and <mux_dec>
+            if(tmp){
+                /* Match names */
+                for (j = 0; j < NumSwitches; ++j) {
+                    if (0 == strcmp(tmp, Switches[j].name.c_str())) {
+                        break; /* End loop so j is where we want it */
+                    }
                 }
+                if (j >= NumSwitches) {
+                    archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem),
+                                "'%s' is not a valid mux name.\n", tmp);
+                }
+
+                /* Unidir muxes must have the same switch
+                * for wire and opin fanin since there is
+                * really only the mux in unidir. */
+                Segs[i].arch_wire_switch = j;
+                Segs[i].arch_opin_switch = j;
             }
-            if (j >= NumSwitches) {
-                archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem),
-                               "'%s' is not a valid mux name.\n", tmp);
-            }
+            else { //if a general mux is not defined, we should look for specific mux for each direction in the architecture file
+                SubElem = get_single_child(Node, "mux_inc", loc_data, ReqOpt::OPTIONAL);
+                tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
+                if(!tmp){
+                    archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem),
+                                "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified");
+                } else{
+                    /* Match names */
+                    for (j = 0; j < NumSwitches; ++j) {
+                        if (0 == strcmp(tmp, Switches[j].name.c_str())) {
+                            break; /* End loop so j is where we want it */
+                        }
+                    }
+                    if (j >= NumSwitches) {
+                        archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem),
+                                    "'%s' is not a valid mux name.\n", tmp);
+                    }
 
-            /* Unidir muxes must have the same switch
-             * for wire and opin fanin since there is
-             * really only the mux in unidir. */
-            Segs[i].arch_wire_switch = j;
-            Segs[i].arch_opin_switch = j;
+                    /* Unidir muxes must have the same switch
+                    * for wire and opin fanin since there is
+                    * really only the mux in unidir. */
+                    Segs[i].arch_wire_switch = j;
+                    Segs[i].arch_opin_switch = j;
+                }
 
-        }
+                SubElem = get_single_child(Node, "mux_dec", loc_data, ReqOpt::OPTIONAL);
+                tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
+                if(!tmp){
+                    archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem),
+                                "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified");
+                } else{
+                    /* Match names */
+                    for (j = 0; j < NumSwitches; ++j) {
+                        if (0 == strcmp(tmp, Switches[j].name.c_str())) {
+                            break; /* End loop so j is where we want it */
+                        }
+                    }
+                    if (j >= NumSwitches) {
+                        archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem),
+                                    "'%s' is not a valid mux name.\n", tmp);
+                    }
 
+                    /* Unidir muxes must have the same switch
+                    * for wire and opin fanin since there is
+                    * really only the mux in unidir. */
+                    Segs[i].arch_wire_switch_dec = j;
+                    Segs[i].arch_opin_switch_dec = j;
+                }
+            }
+        }
         else {
             VTR_ASSERT(BI_DIRECTIONAL == Segs[i].directionality);
             SubElem = get_single_child(Node, "wire_switch", loc_data);

vpr/src/route/rr_graph2.cpp

@@ -300,7 +300,8 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width,
      *     as they will not be staggered by different segment start points.     */
 
     int cur_track, ntracks, itrack, length, j, index;
-    int arch_wire_switch, arch_opin_switch, fac, num_sets, tmp;
+    int fac, num_sets, tmp;
+    int arch_wire_switch, arch_opin_switch, arch_wire_switch_dec, arch_opin_switch_dec;
     int arch_opin_between_dice_switch;
     int group_start, first_track;
     std::unique_ptr<int[]> sets_per_seg_type;
@@ -352,8 +353,10 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width,
 
         arch_wire_switch = segment_inf[i].arch_wire_switch;
         arch_opin_switch = segment_inf[i].arch_opin_switch;
+        arch_wire_switch_dec = segment_inf[i].arch_wire_switch_dec;
+        arch_opin_switch_dec = segment_inf[i].arch_opin_switch_dec;
         arch_opin_between_dice_switch = segment_inf[i].arch_opin_between_dice_switch;
-        VTR_ASSERT((arch_wire_switch == arch_opin_switch) || (directionality != UNI_DIRECTIONAL));
+        VTR_ASSERT((arch_wire_switch == arch_opin_switch && arch_wire_switch_dec == arch_opin_switch_dec) || (directionality != UNI_DIRECTIONAL));
 
         /* Set up the tracks of same type */
         group_start = 0;
@@ -416,8 +419,6 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width,
             seg_details[cur_track].Cmetal = segment_inf[i].Cmetal;
             //seg_details[cur_track].Cmetal_per_m = segment_inf[i].Cmetal_per_m;
 
-            seg_details[cur_track].arch_wire_switch = arch_wire_switch;
-            seg_details[cur_track].arch_opin_switch = arch_opin_switch;
             seg_details[cur_track].arch_opin_between_dice_switch = arch_opin_between_dice_switch;
 
             if (BI_DIRECTIONAL == directionality) {
@@ -427,6 +428,18 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width,
                 seg_details[cur_track].direction = (itrack % 2) ? Direction::DEC : Direction::INC;
             }
 
+            //check for directionality to set the wire_switch and opin_switch
+            //if not specified in the architecture file, we will use a same mux for both directions
+            if (seg_details[cur_track].direction == Direction::INC || seg_details[cur_track].direction == Direction::BIDIR || arch_wire_switch_dec == -1){
+                seg_details[cur_track].arch_opin_switch = arch_opin_switch;
+                seg_details[cur_track].arch_wire_switch = arch_wire_switch;
+            }
+            else {
+                VTR_ASSERT(seg_details[cur_track].direction == Direction::DEC);
+                seg_details[cur_track].arch_opin_switch = arch_opin_switch_dec;
+                seg_details[cur_track].arch_wire_switch = arch_wire_switch_dec;
+            }
+
             seg_details[cur_track].index = i;
             seg_details[cur_track].abs_index = segment_inf[i].seg_index;