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Fix for #100 #107

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merged 2 commits into from
Nov 16, 2022
Merged

Fix for #100 #107

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4b337ad
Add check for scalar source operand validity
Oct 18, 2022
d58c0bc
Move source_reg_valid logic from core to decoder
Nov 8, 2022
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39 changes: 37 additions & 2 deletions rtl/vproc_core.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -286,10 +286,45 @@ module vproc_core import vproc_pkg::*; #(
end
assign dec_buf_valid_d = (~dec_ready | dec_valid) & ~dec_clear;

// Check if scalar source operands are valid
logic source_xreg_valid;
logic [31:0] instr;
assign instr = xif_issue_if.issue_req.instr;

always_comb begin
source_xreg_valid = 1'b1;
if (instr[6:0] == 7'h57) begin
unique case (instr[14:12])
// rs1 must be valid for OPIVX and OPMVX
3'b100,
3'b110: begin
source_xreg_valid = xif_issue_if.issue_req.rs_valid[0];
end
3'b111: begin
// rs1 must be valid for vsetvli
if (instr[31:30] == 2'b11) begin
source_xreg_valid = xif_issue_if.issue_req.rs_valid[0];
// rs1 and rs2 must be valid for vsetvl
end else if (instr[31] == 1'b0) begin
source_xreg_valid = xif_issue_if.issue_req.rs_valid[0] & xif_issue_if.issue_req.rs_valid[1];
end
end
default: source_xreg_valid = 1'b1;
endcase
// rs1 must be valid for all load and store instructions
end else if (instr[6:0] == 7'h27 || instr[6:0] == 7'h07) begin
source_xreg_valid = xif_issue_if.issue_req.rs_valid[0];
// rs1 and rs2 must be valid for strided load and store instructions
if (instr[27:26] == 2'b10) begin
source_xreg_valid = xif_issue_if.issue_req.rs_valid[0] & xif_issue_if.issue_req.rs_valid[1];
end
end
end
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The decoder module uses similar nested case statements, maybe this could partially be moved to the decoder module. You could, for instance, add two output signals named needs_rs1 and needs_rs2 to the decoder and then assign source_xreg_valid in the core module as follows:

assign source_xreg_valid = (~needs_rs1 | xif_issue_if.issue_req.rs_valid[0]) & (~needs_rs2 | xif_issue_if.issue_req.rs_valid[1]);


// Stall instruction offloading in case the instruction ID is already used
// by another instruction which is not complete
logic instr_valid, issue_id_used;
assign instr_valid = xif_issue_if.issue_valid & ~issue_id_used;
assign instr_valid = xif_issue_if.issue_valid & ~issue_id_used & source_xreg_valid;

op_unit instr_unit;
op_mode instr_mode;
Expand Down Expand Up @@ -331,7 +366,7 @@ module vproc_core import vproc_pkg::*; #(
// vset[i]vl[i] instruction that will change the configuration in the next
// cycle and any subsequent offloaded instruction must be validated w.r.t.
// the new configuration.
assign xif_issue_if.issue_ready = dec_ready & ~issue_id_used;
assign xif_issue_if.issue_ready = dec_ready & ~issue_id_used & source_xreg_valid;

assign xif_issue_if.issue_resp.accept = dec_valid;
assign xif_issue_if.issue_resp.writeback = dec_valid & (((instr_unit == UNIT_ELEM) & instr_mode.elem.xreg) | (instr_unit == UNIT_CFG));
Expand Down