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clean-up
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@awatterott
awatterott committed Dec 15, 2019
1 parent 3ed2913 commit e4dd4dc
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Showing 6 changed files with 45 additions and 46 deletions.
2 changes: 1 addition & 1 deletion hardware/atmega328pb/avr/libraries/Wire/src/Wire.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,7 @@ uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint32_t iaddres
// write internal register address - most significant byte first
while (isize-- > 0)
write((uint8_t)(iaddress >> (isize*8)));
endTransmission(false);
endTransmission(false);
}

// clamp to buffer length
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2 changes: 1 addition & 1 deletion hardware/atmega328pb/avr/libraries/Wire/src/Wire.h
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ class TwoWire : public Stream
uint8_t endTransmission(uint8_t);
uint8_t requestFrom(uint8_t, uint8_t);
uint8_t requestFrom(uint8_t, uint8_t, uint8_t);
uint8_t requestFrom(uint8_t, uint8_t, uint32_t, uint8_t, uint8_t);
uint8_t requestFrom(uint8_t, uint8_t, uint32_t, uint8_t, uint8_t);
uint8_t requestFrom(int, int);
uint8_t requestFrom(int, int, int);
virtual size_t write(uint8_t);
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40 changes: 20 additions & 20 deletions hardware/atmega328pb/avr/libraries/Wire/src/utility/twi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -399,16 +399,16 @@ ISR(TWI_vect)
TWDR = twi_masterBuffer[twi_masterBufferIndex++];
twi_reply(1);
}else{
if (twi_sendStop)
if (twi_sendStop)
twi_stop();
else {
twi_inRepStart = true; // we're gonna send the START
// don't enable the interrupt. We'll generate the start, but we
// avoid handling the interrupt until we're in the next transaction,
// at the point where we would normally issue the start.
TWCR = _BV(TWINT) | _BV(TWSTA)| _BV(TWEN) ;
twi_state = TWI_READY;
}
else {
twi_inRepStart = true; // we're gonna send the START
// don't enable the interrupt. We'll generate the start, but we
// avoid handling the interrupt until we're in the next transaction,
// at the point where we would normally issue the start.
TWCR = _BV(TWINT) | _BV(TWSTA)| _BV(TWEN) ;
twi_state = TWI_READY;
}
}
break;
case TW_MT_SLA_NACK: // address sent, nack received
Expand Down Expand Up @@ -439,17 +439,17 @@ ISR(TWI_vect)
case TW_MR_DATA_NACK: // data received, nack sent
// put final byte into buffer
twi_masterBuffer[twi_masterBufferIndex++] = TWDR;
if (twi_sendStop)
twi_stop();
else {
twi_inRepStart = true; // we're gonna send the START
// don't enable the interrupt. We'll generate the start, but we
// avoid handling the interrupt until we're in the next transaction,
// at the point where we would normally issue the start.
TWCR = _BV(TWINT) | _BV(TWSTA)| _BV(TWEN) ;
twi_state = TWI_READY;
}
break;
if (twi_sendStop)
twi_stop();
else {
twi_inRepStart = true; // we're gonna send the START
// don't enable the interrupt. We'll generate the start, but we
// avoid handling the interrupt until we're in the next transaction,
// at the point where we would normally issue the start.
TWCR = _BV(TWINT) | _BV(TWSTA)| _BV(TWEN) ;
twi_state = TWI_READY;
}
break;
case TW_MR_SLA_NACK: // address sent, nack received
twi_stop();
break;
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2 changes: 1 addition & 1 deletion hardware/atmega328pb/avr/libraries/Wire1/src/Wire1.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -107,7 +107,7 @@ uint8_t TwoWire1::requestFrom(uint8_t address, uint8_t quantity, uint32_t iaddre
// write internal register address - most significant byte first
while (isize-- > 0)
write((uint8_t)(iaddress >> (isize*8)));
endTransmission(false);
endTransmission(false);
}

// clamp to buffer length
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2 changes: 1 addition & 1 deletion hardware/atmega328pb/avr/libraries/Wire1/src/Wire1.h
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ class TwoWire1 : public Stream
uint8_t endTransmission(uint8_t);
uint8_t requestFrom(uint8_t, uint8_t);
uint8_t requestFrom(uint8_t, uint8_t, uint8_t);
uint8_t requestFrom(uint8_t, uint8_t, uint32_t, uint8_t, uint8_t);
uint8_t requestFrom(uint8_t, uint8_t, uint32_t, uint8_t, uint8_t);
uint8_t requestFrom(int, int);
uint8_t requestFrom(int, int, int);
virtual size_t write(uint8_t);
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43 changes: 21 additions & 22 deletions hardware/atmega328pb/avr/libraries/Wire1/src/utility/twi1.c
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Original file line number Diff line number Diff line change
Expand Up @@ -381,8 +381,7 @@ void twi_releaseBus1(void)

ISR(TWI1_vect)
{
// #define TW_STATUS (TWSR & TW_STATUS_MASK)
switch(TWSR1 & TW_STATUS_MASK){
switch(TWSR1 & TW_STATUS_MASK){ // #define TW_STATUS (TWSR & TW_STATUS_MASK)
// All Master
case TW_START: // sent start condition
case TW_REP_START: // sent repeated start condition
Expand All @@ -400,16 +399,16 @@ ISR(TWI1_vect)
TWDR1 = twi_masterBuffer[twi_masterBufferIndex++];
twi_reply1(1);
}else{
if (twi_sendStop)
if (twi_sendStop)
twi_stop1();
else {
twi_inRepStart = true; // we're gonna send the START
// don't enable the interrupt. We'll generate the start, but we
// avoid handling the interrupt until we're in the next transaction,
// at the point where we would normally issue the start.
TWCR1 = _BV(TWINT) | _BV(TWSTA)| _BV(TWEN) ;
twi_state = TWI_READY;
}
else {
twi_inRepStart = true; // we're gonna send the START
// don't enable the interrupt. We'll generate the start, but we
// avoid handling the interrupt until we're in the next transaction,
// at the point where we would normally issue the start.
TWCR1 = _BV(TWINT) | _BV(TWSTA)| _BV(TWEN) ;
twi_state = TWI_READY;
}
}
break;
case TW_MT_SLA_NACK: // address sent, nack received
Expand Down Expand Up @@ -440,17 +439,17 @@ ISR(TWI1_vect)
case TW_MR_DATA_NACK: // data received, nack sent
// put final byte into buffer
twi_masterBuffer[twi_masterBufferIndex++] = TWDR1;
if (twi_sendStop)
twi_stop1();
else {
twi_inRepStart = true; // we're gonna send the START
// don't enable the interrupt. We'll generate the start, but we
// avoid handling the interrupt until we're in the next transaction,
// at the point where we would normally issue the start.
TWCR1 = _BV(TWINT) | _BV(TWSTA)| _BV(TWEN) ;
twi_state = TWI_READY;
}
break;
if (twi_sendStop)
twi_stop1();
else {
twi_inRepStart = true; // we're gonna send the START
// don't enable the interrupt. We'll generate the start, but we
// avoid handling the interrupt until we're in the next transaction,
// at the point where we would normally issue the start.
TWCR1 = _BV(TWINT) | _BV(TWSTA)| _BV(TWEN) ;
twi_state = TWI_READY;
}
break;
case TW_MR_SLA_NACK: // address sent, nack received
twi_stop1();
break;
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