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  • Sophgo
  • Shanghai

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wenxxxxfu/README.md

Hi there 👋

My name is Finn Fu. I received my PhD from the Institute of Microelectronics, Chinese Academy of Sciences, and now work as a logic design engineer in Sophgo.

  • ✏️ Python / C / C++ / Verilog / SystemVerilog
  • 🌱 During PhD, my research interests include few-shot learning, self-supervised learning, and medical image processing. Now, my work is related to computer architecture.
  • ⭐ I have a wide range of interests, including reading, hiking and watching movies, and I want to try more areas that I have never covered in the future.
  • 📧 contact me by: [email protected]
github contribution grid snake animation

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  1. wenxxxxfu wenxxxxfu Public

    Config files for my GitHub profile.

  2. common_digital_modules common_digital_modules Public

    common digital modules implemented by verilog/systemverilog

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  3. OpenMIPS OpenMIPS Public

    a cpu core base on MIPS, follwing the book《自己动手写CPU》

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  4. vim_config_for_SystemVerilog vim_config_for_SystemVerilog Public

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    Vim syntax etc for Verilog and SystemVerilog

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