Initial Release
billphipps
released this
05 Oct 14:17
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57 commits
to main
since this release
Initial release after internal and early evaluator testing. Due to NDA restrictions, access to the Infineon and ST Micro ports is limited. Please contact [email protected] for access.
New Feature Additions
- POSIX simulator and test environment
- Memory fencing and cache controls for memory transport
- Support for Aurix Tricore TC3xx and ST SPC58NN
- DMA support for SHA2 and NVM objects
- Cancellation for CMAC
- Support NO_MALLOC and STATIC_MEMORY
- SHE+ interface
Enhancements and Optimizations
- Reduction in static server memory requirements
- Hardware offload for AURIX and ST C3 modules