x86/intel: optional build of TSX support

Transactional Synchronization Extensions are supported on certain Intel's CPUs only, hence can be put under CONFIG_INTEL build option. The whole TSX support, even if supported by CPU, may need to be disabled via options, by microcode or through spec-ctrl, depending on a set of specific conditions. To make sure nothing gets accidentally runtime-broken all modifications of global TSX configuration variables is secured by #ifdef's, while variables themselves redefined to 0, so that ones can't mistakenly be written to. Signed-off-by: Sergiy Kibrik <[email protected]> Acked-by: Jan Beulich <[email protected]>
xcp-ng · Aug 1, 2024 · b1b017f · b1b017f
1 parent fb45a35
commit b1b017f
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Showing 4 changed files with 12 additions and 2 deletions.
diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
@@ -2586,7 +2586,7 @@ pages) must also be specified via the tbuf_size parameter.
 ### tsx
     = <bool>
 
-    Applicability: x86
+    Applicability: x86 with CONFIG_INTEL active
     Default: false on parts vulnerable to TAA, true otherwise
 
 Controls for the use of Transactional Synchronization eXtensions.

diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile
@@ -67,7 +67,7 @@ obj-y += srat.o
 obj-y += string.o
 obj-y += time.o
 obj-y += traps.o
-obj-y += tsx.o
+obj-$(CONFIG_INTEL) += tsx.o
 obj-y += usercopy.o
 obj-y += x86_emulate.o
 obj-$(CONFIG_TBOOT) += tboot.o

diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/asm/processor.h
@@ -503,9 +503,15 @@ static inline uint8_t get_cpu_family(uint32_t raw, uint8_t *model,
     return fam;
 }
 
+#ifdef CONFIG_INTEL
 extern int8_t opt_tsx;
 extern bool rtm_disabled;
 void tsx_init(void);
+#else
+#define opt_tsx      0     /* explicitly indicate TSX is off */
+#define rtm_disabled false /* RTM was not force-disabled */
+static inline void tsx_init(void) {}
+#endif
 
 void update_mcu_opt_ctrl(void);
 void set_in_mcu_opt_ctrl(uint32_t mask, uint32_t val);

diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
@@ -116,8 +116,10 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             if ( opt_pv_l1tf_domu < 0 )
                 opt_pv_l1tf_domu = 0;
 
+#ifdef CONFIG_INTEL
             if ( opt_tsx == -1 )
                 opt_tsx = -3;
+#endif
 
         disable_common:
             opt_rsb_pv = false;
@@ -2264,13 +2266,15 @@ void __init init_speculation_mitigations(void)
      * plausibly value TSX higher than Hyperthreading...), disable TSX to
      * mitigate TAA.
      */
+#ifdef CONFIG_INTEL
     if ( opt_tsx == -1 && cpu_has_bug_taa && cpu_has_tsx_ctrl &&
          ((hw_smt_enabled && opt_smt) ||
           !boot_cpu_has(X86_FEATURE_SC_VERW_IDLE)) )
     {
         opt_tsx = 0;
         tsx_init();
     }
+#endif
 
     /*
      * On some SRBDS-affected hardware, it may be safe to relax srb-lock by