Merge branch 'master' into v3

CMakeLists.txt

@@ -3,7 +3,7 @@ project(capstone)
 
 set(VERSION_MAJOR 3)
 set(VERSION_MINOR 0)
-set(VERSION_PATCH 2)
+set(VERSION_PATCH 3)
 
 # to configure the options specify them in in the command line or change them in the cmake UI.
 # Don't edit the makefile!

ChangeLog

@@ -1,5 +1,42 @@
 This file details the changelog of Capstone.
 
+---------------------------------
+Version 3.0.3: May 08th, 2015
+
+
+[ Library ]
+
+- Support to embed into Mac OS X kernel extensions.
+- Now it is possible to compile Capstone with older C compilers, such as
+  GCC 4.8 on Ubuntu 12.04.
+- Add "test_iter" to MSVC project.
+
+
+[ X86 ]
+
+- All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
+  $1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of
+  "rcll %edx").
+- CMPXCHG16B is a valid instruction with LOCK prefix.
+- Fixed a segfault on the input of 0xF3.
+
+
+[ Arm ]
+
+- BLX instruction modifies PC & LR registers.
+
+
+[ Sparc ]
+
+- Improved displacement decoding for sparc banching instructions.
+
+
+[ Python binding ]
+
+- Fix for Cython so it can properly initialize.
+- X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type.
+- Properly support compile with Cygwin & install binding (setup.py).
+
 ---------------------------------
 Version 3.0.2: March 11th, 2015
 

RELEASE_NOTES

@@ -0,0 +1,2 @@
+This version 3.0.3 is dedicated to Prof. Yoshiyasu Takefuji, my former advisor,
+who is turning 60 years old this year 2015!

arch/ARM/ARMMapping.c

@@ -440,7 +440,7 @@ static insn_map insns[] = {
 	{
 		ARM_BLXi, ARM_INS_BLX,
 #ifndef CAPSTONE_DIET
-		{ 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0
+		{ ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_JUMP, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0
 #endif
 	},
 	{
@@ -11712,13 +11712,13 @@ static insn_map insns[] = {
 #endif
 	},
 	{
-		ARM_t2MOVsra_flag, ARM_INS_ASRS,
+		ARM_t2MOVsra_flag, ARM_INS_ASR,
 #ifndef CAPSTONE_DIET
 		{ 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
 #endif
 	},
 	{
-		ARM_t2MOVsrl_flag, ARM_INS_LSRS,
+		ARM_t2MOVsrl_flag, ARM_INS_LSR,
 #ifndef CAPSTONE_DIET
 		{ 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
 #endif
@@ -12738,7 +12738,7 @@ static insn_map insns[] = {
 #endif
 	},
 	{
-		ARM_t2SUBS_PC_LR, ARM_INS_SUBS,
+		ARM_t2SUBS_PC_LR, ARM_INS_SUB,
 #ifndef CAPSTONE_DIET
 		{ 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
 #endif
@@ -13332,7 +13332,7 @@ static insn_map insns[] = {
 #endif
 	},
 	{
-		ARM_tMOVSr, ARM_INS_MOVS,
+		ARM_tMOVSr, ARM_INS_MOV,
 #ifndef CAPSTONE_DIET
 		{ 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
 #endif

arch/X86/X86ATTInstPrinter.c

@@ -675,6 +675,83 @@ void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info)
 	}
 
 	if (MI->csh->detail) {
+        // some instructions need to supply immediate 1 in the first op
+        switch(MCInst_getOpcode(MI)) {
+            default:
+                break;
+            case X86_SHL8r1:
+            case X86_SHL16r1:
+            case X86_SHL32r1:
+            case X86_SHL64r1:
+            case X86_SAL8r1:
+            case X86_SAL16r1:
+            case X86_SAL32r1:
+            case X86_SAL64r1:
+            case X86_SHR8r1:
+            case X86_SHR16r1:
+            case X86_SHR32r1:
+            case X86_SHR64r1:
+            case X86_SAR8r1:
+            case X86_SAR16r1:
+            case X86_SAR32r1:
+            case X86_SAR64r1:
+            case X86_RCL8r1:
+            case X86_RCL16r1:
+            case X86_RCL32r1:
+            case X86_RCL64r1:
+            case X86_RCR8r1:
+            case X86_RCR16r1:
+            case X86_RCR32r1:
+            case X86_RCR64r1:
+            case X86_ROL8r1:
+            case X86_ROL16r1:
+            case X86_ROL32r1:
+            case X86_ROL64r1:
+            case X86_ROR8r1:
+            case X86_ROR16r1:
+            case X86_ROR32r1:
+            case X86_ROR64r1:
+            case X86_SHL8m1:
+            case X86_SHL16m1:
+            case X86_SHL32m1:
+            case X86_SHL64m1:
+            case X86_SAL8m1:
+            case X86_SAL16m1:
+            case X86_SAL32m1:
+            case X86_SAL64m1:
+            case X86_SHR8m1:
+            case X86_SHR16m1:
+            case X86_SHR32m1:
+            case X86_SHR64m1:
+            case X86_SAR8m1:
+            case X86_SAR16m1:
+            case X86_SAR32m1:
+            case X86_SAR64m1:
+            case X86_RCL8m1:
+            case X86_RCL16m1:
+            case X86_RCL32m1:
+            case X86_RCL64m1:
+            case X86_RCR8m1:
+            case X86_RCR16m1:
+            case X86_RCR32m1:
+            case X86_RCR64m1:
+            case X86_ROL8m1:
+            case X86_ROL16m1:
+            case X86_ROL32m1:
+            case X86_ROL64m1:
+            case X86_ROR8m1:
+            case X86_ROR16m1:
+            case X86_ROR32m1:
+            case X86_ROR64m1:
+                // shift all the ops right to leave 1st slot for this new register op
+                memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]),
+                        sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1));
+                MI->flat_insn->detail->x86.operands[0].type = X86_OP_IMM;
+                MI->flat_insn->detail->x86.operands[0].imm = 1;
+                MI->flat_insn->detail->x86.operands[0].size = 1;
+                MI->flat_insn->detail->x86.op_count++;
+        }
+
 		// special instruction needs to supply register op
 		// first op can be embedded in the asm by llvm.
 		// so we have to add the missing register as the first operand