This repo is currently a work in progress nothing is currently yet working!
This repo contains documentation of various FPGA architectures, it is currently concentrating on;
- Lattice iCE40
- Artix 7
The aim is to include useful documentation (both human and machine readable) on the primitives and routing infrastructure for these architectures. We hope this enables growth in the open source FPGA tools space.
The repo includes;
- Black box part definitions
- Verilog simulations
- Verilog To Routing architecture definitions
- Documentation for humans
The documentation can be generated using Sphinx.
Make sure git submodules are cloned:
git submodule init
git submodule update
Run the full suite:
make
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yosys Verilog parsing and synthesis.
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vtr Place and route tool.
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iverilog Very correct FOSS Verilog Simulator
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verilator Fast FOSS Verilog Simulator
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sphinx Tool for generating nice looking documentation.
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breathe Tool for allowing Doxygen and Sphinx integration.
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doxygen-verilog Allows using Doxygen style comments inside Verilog files.
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netlistsvg Tool for generating nice logic diagrams from Verilog code.
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symbolator Tool for generating symbol diagrams from Verilog (and VHDL) code.
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wavedrom Tool for generating waveform / timing diagrams.