hwspinlock/msm: Add snapshot of remote_spinlock driver

This is a snapshot of the msm remote_spinlock driver as of msm-4.4
commit <aaf356abef2> (Merge "scsi: ufs: add 2 lane support").

In addition, fix coding style issues and add comments to memory
barriers.

CRs-Fixed: 1059650
Change-Id: Ib907647e38fbd7c6bcdc724a92518959431da56e
Signed-off-by: Chris Lew <[email protected]>

Documentation/devicetree/bindings/arm/msm/ipc-spinlock.txt

@@ -0,0 +1,27 @@
+Qualcomm Technologies inc Interprocessor Communication Spinlock
+
+--Dedicated Hardware Implementation--
+Required properties:
+- compatible : should be "qcom,ipc-spinlock-sfpb"
+- reg : the location and size of the spinlock hardware
+- qcom,num-locks : the number of locks supported
+
+Example:
+
+	qcom,ipc-spinlock@fd484000 {
+		compatible = "qcom,ipc-spinlock-sfpb";
+		reg = <0xfd484000 0x1000>;
+		qcom,num-locks = <32>;
+	};
+
+--LDREX Implementation--
+Required properties:
+- compatible : should be "qcom,ipc-spinlock-ldrex"
+- reg : the location and size of the shared lock memory
+
+Example:
+
+	qcom,ipc-spinlock@fa00000 {
+		compatible = "qcom,ipc-spinlock-ldrex";
+		reg = <0xfa00000 0x200000>;
+	};

drivers/hwspinlock/Kconfig

@@ -53,4 +53,15 @@ config HSEM_U8500
 
 	  If unsure, say N.
 
+config REMOTE_SPINLOCK_MSM
+	bool "MSM Remote Spinlock Functionality"
+	depends on ARCH_QCOM
+	select HWSPINLOCK
+	help
+	  Say y here to support the MSM Remote Spinlock functionality, which
+	  provides a synchronisation mechanism for the various processor on the
+	  SoC.
+
+	  If unsure, say N.
+
 endmenu

drivers/hwspinlock/Makefile

@@ -7,3 +7,4 @@ obj-$(CONFIG_HWSPINLOCK_OMAP)		+= omap_hwspinlock.o
 obj-$(CONFIG_HWSPINLOCK_QCOM)		+= qcom_hwspinlock.o
 obj-$(CONFIG_HWSPINLOCK_SIRF)		+= sirf_hwspinlock.o
 obj-$(CONFIG_HSEM_U8500)		+= u8500_hsem.o
+obj-$(CONFIG_REMOTE_SPINLOCK_MSM)	+= msm_remote_spinlock.o