Skip to content

Commit

Permalink
Finish everything
Browse files Browse the repository at this point in the history
  • Loading branch information
@LucasSte
LucasSte committed Dec 13, 2024
1 parent 27db3d8 commit 0243fe9
Show file tree
Hide file tree
Showing 6 changed files with 30 additions and 137 deletions.
123 changes: 3 additions & 120 deletions llvm/lib/Target/SBF/SBFMIPeephole.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -57,8 +57,6 @@ struct SBFMIPeephole : public MachineFunctionPass {
bool isPhiFrom32Def(MachineInstr *MovMI);
bool isMovFrom32Def(MachineInstr *MovMI);
bool eliminateZExt();
bool simplifySExt();
bool simplifyZExt();

std::set<MachineInstr *> PhiInsns;

Expand All @@ -71,7 +69,7 @@ struct SBFMIPeephole : public MachineFunctionPass {

initialize(MF);

return simplifySExt() || simplifyZExt() || eliminateZExt();
return eliminateZExt();
}
};

Expand Down Expand Up @@ -168,121 +166,6 @@ bool SBFMIPeephole::isMovFrom32Def(MachineInstr *MovMI)
return true;
}

bool SBFMIPeephole::simplifyZExt() {
MachineInstr* ToErase = nullptr;
bool Eliminated = false;
for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {

// If the previous instruction was marked for elimination, remove it now.
if (ToErase) {
ToErase->eraseFromParent();
ToErase = nullptr;
}

// Eliminate the 32-bit to 64-bit sign extension sequence when we are
// emulating 32-bit arithmetics with ALU64 instructions.
//
// MOV64 rB, rA
// SLL_ri rB, rB, 32
// SRR_ri rB, rB, 32
if (MI.getOpcode() == SBF::SRL_ri &&
MI.getOperand(2).getImm() == 32) {
Register DstReg = MI.getOperand(0).getReg();
Register ShfReg = MI.getOperand(1).getReg();
MachineInstr *SllMI = MRI->getVRegDef(ShfReg);

LLVM_DEBUG(dbgs() << "Starting SRA_ri found:");
LLVM_DEBUG(MI.dump());
if (!SllMI ||
SllMI->isPHI() ||
SllMI->getOpcode() != SBF::SLL_ri ||
SllMI->getOperand(2).getImm() != 32)
continue;
LLVM_DEBUG(dbgs() << " SLL found:");
LLVM_DEBUG(SllMI->dump());

MachineInstr *PrevMI = MRI->getVRegDef(SllMI->getOperand(1).getReg());
if (!PrevMI ||
PrevMI->isPHI())
continue;

Register SrcReg = PrevMI->getOperand(0).getReg();
BuildMI(MBB, MI, MI.getDebugLoc(),
TII->get(SBF::AND_32_zero_ext), DstReg)
.addReg(SrcReg).addImm(0xffffffff);

SllMI->eraseFromParent();
ToErase = &MI;
Eliminated = true;
}
}
}
return Eliminated;
}

bool SBFMIPeephole::simplifySExt() {
MachineInstr* ToErase = nullptr;
bool Eliminated = false;
for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {

// If the previous instruction was marked for elimination, remove it now.
if (ToErase) {
ToErase->eraseFromParent();
ToErase = nullptr;
}

// Eliminate the 32-bit to 64-bit sign extension sequence when we are
// emulating 32-bit arithmetics with ALU64 instructions.
//
// MOV64 rB, rA
// SLL_ri rB, rB, 32
// SRA_ri rB, rB, 32
if (MI.getOpcode() == SBF::SRA_ri &&
MI.getOperand(2).getImm() == 32) {
Register DstReg = MI.getOperand(0).getReg();
Register ShfReg = MI.getOperand(1).getReg();
MachineInstr *SllMI = MRI->getVRegDef(ShfReg);

LLVM_DEBUG(dbgs() << "Starting SRA_ri found:");
LLVM_DEBUG(MI.dump());
if (!SllMI ||
SllMI->isPHI() ||
SllMI->getOpcode() != SBF::SLL_ri ||
SllMI->getOperand(2).getImm() != 32)
continue;
LLVM_DEBUG(dbgs() << " SLL found:");
LLVM_DEBUG(SllMI->dump());

MachineInstr *MovMI = MRI->getVRegDef(SllMI->getOperand(1).getReg());
if (!MovMI ||
MovMI->isPHI() ||
(MovMI->getOpcode() != SBF::COPY &&
MovMI->getOpcode() != SBF::MOV_rr))
continue;

if (!isMovFrom32Def(MovMI)) {
LLVM_DEBUG(dbgs()
<< " One SExt elim sequence failed qualifying elim.\n");
continue;
}

Register SubReg = MovMI->getOperand(1).getReg();
BuildMI(MBB, MI, MI.getDebugLoc(),
TII->get(SBF::MOV_64_sign_ext), DstReg)
.addReg(SubReg);

SllMI->eraseFromParent();
MovMI->eraseFromParent();
ToErase = &MI;
Eliminated = true;
}
}
}
return Eliminated;
}

bool SBFMIPeephole::eliminateZExt() {
MachineInstr* ToErase = nullptr;
bool Eliminated = false;
Expand All @@ -303,8 +186,8 @@ bool SBFMIPeephole::eliminateZExt() {
LLVM_DEBUG(dbgs() << "Candidate MOV_32_64_no_sext instruction:");
LLVM_DEBUG(MI.dump());

if (!isMovFrom32Def(&MI))
continue;
// if (!isMovFrom32Def(&MI))
// continue;

LLVM_DEBUG(dbgs() << "Removing the MOV_32_64_no_sext instruction\n");

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/SBF/SBFTargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -160,7 +160,7 @@ void SBFPassConfig::addMachineSSAOptimization() {

const SBFSubtarget *Subtarget = getSBFTargetMachine().getSubtargetImpl();
if (!DisableMIPeephole) {
if (Subtarget->getHasExplicitSignExt())
if (Subtarget->getHasAlu32() && Subtarget->getHasExplicitSignExt())
addPass(createSBFMIPeepholePass());
addPass(createSBFMIPeepholeTruncElimPass());
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SBF/32-bit-subreg-cond-select.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -56,8 +56,8 @@ entry:
ret i32 %c.d
}
; CHECK-LABEL: select_cc_32
; CHECK: mov64 r{{[0-9]+}}, w{{[0-9]+}}
; CHECK: mov64 r{{[0-9]+}}, w{{[0-9]+}}
; CHECK-NOT: mov64 r{{[0-9]+}}, w{{[0-9]+}}
; CHECK-NOT: mov64 r{{[0-9]+}}, w{{[0-9]+}}
; CHECK: jgt r{{[0-9]+}}, r{{[0-9]+}}
; CHECK-NOT: lsh64 r{{[0-9]+}}, 32
; CHECK-NOT: rsh64 r{{[0-9]+}}, 32
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/SBF/atomics_sbf.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -68,7 +68,7 @@ entry:
; CHECK-LABEL: test_cas_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK-NOT: mov64 r4, w0
; CHECK: mov64 r2, w2
; CHECK-NOT: mov64 r2, w2
; CHECK: jeq r0, r2,
; CHECK: mov64 w3, w0
; CHECK: stxw [r1 + 0], w3
Expand Down Expand Up @@ -235,10 +235,10 @@ entry:

; CHECK-LABEL: test_umin_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK: mov64 r4, w2
; CHECK-NOT: mov64 r4, w2
; CHECK-NOT: mov64 r5, w0
; CHECK: mov64 w3, w0
; CHECK: jgt r4, r0,
; CHECK: jgt r2, r0,
; CHECK: mov64 w3, w2
; CHECK: stxw [r1 + 0], w3
define dso_local i32 @test_umin_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 {
Expand All @@ -262,9 +262,9 @@ entry:
; CHECK-LABEL: test_umax_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK-NOT: mov64 r4, w0
; CHECK: mov64 r4, w2
; CHECK-NOT: mov64 r4, w2
; CHECK: mov64 w3, w0
; CHECK: jgt r0, r4
; CHECK: jgt r0, r2
; CHECK: mov64 w3, w2
; CHECK: stxw [r1 + 0], w3
define dso_local i32 @test_umax_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 {
Expand Down Expand Up @@ -331,7 +331,7 @@ entry:
; CHECK-LABEL: test_weak_cas_32
; CHECK: ldxw w4, [r1 + 0]
; CHECK-NOT: mov64 r5, w4
; CHECK: mov64 r2, w2
; CHECK-NOT: mov64 r2, w2
; CHECK: jeq r4, r2,
; CHECK: stxw [r1 + 0], w3
define dso_local void @test_weak_cas_32(i32* nocapture %p, i32 %old, i32 %new) local_unnamed_addr {
Expand Down
14 changes: 6 additions & 8 deletions llvm/test/CodeGen/SBF/objdump_cond_op.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,9 +25,8 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
%6 = shl i32 %5, 1
%7 = mul i32 %6, %5
br label %13
; CHECK-NOT: lsh64 r1, 0x20
; CHECK-NOT: rsh64 r1, 0x20
; CHECK: and32 w1, -0x1
; CHECK: lsh64 r1, 0x20
; CHECK: rsh64 r1, 0x20
; CHECK: jne r1, 0x2, +0x6 <LBB0_2>

; <label>:8: ; preds = %2
Expand All @@ -40,7 +39,7 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
; CHECK: ldxw r0, [r1 + 0x0]
; CHECK: mul64 r0, r0
; CHECK: lsh64 r0, 0x1
; CHECK: ja +0x6 <LBB0_4>
; CHECK: ja +0x7 <LBB0_4>

; <label>:11: ; preds = %8
%12 = shl nsw i32 %10, 2
Expand All @@ -50,9 +49,8 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
; CHECK: mov32 r3, 0x0
; CHECK: hor64 r3, 0x0
; CHECK: ldxw r0, [r3 + 0x0]
; CHECK-NOT: lsh64 r2, 0x20
; CHECK-NOT: rsh64 r2, 0x20
; CHECK: and32 w2, -0x1
; CHECK: lsh64 r2, 0x20
; CHECK: rsh64 r2, 0x20
; CHECK: jeq r1, r2, +0x4 <LBB0_5>
; CHECK: lsh64 r0, 0x2

Expand All @@ -71,4 +69,4 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
; CHECK-LABEL: <LBB0_5>:
; CHECK: exit
}
attributes #0 = { norecurse nounwind }
attributes #0 = { norecurse nounwind }
12 changes: 12 additions & 0 deletions llvm/test/CodeGen/SBF/peephole-explict-sext.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
; RUN: llc < %s -march=sbf -mattr=+alu32,+explicit-sext | FileCheck %s

define dso_local i32 @select_cc_32(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 {
entry:
; CHECK-LABEL: select_cc_32
%cmp = icmp ugt i32 %a, %b
; CHECK-NOT: mov64 r{{[0-9]+}}, w1
; CHECK-NOT: mov64 r{{[0-9]+}}, w2
; CHECK: jgt r1, r2,
%c.d = select i1 %cmp, i32 %c, i32 %d
ret i32 %c.d
}

0 comments on commit 0243fe9

Please sign in to comment.