arch-riscv: default disable vs bit, set misa with B-ext, update ref-so #25
gem5.yml
on: pull_request
XS-GEM5 - Running test checkpoints
7m 21s
XS-GEM5 - Check memory corruption
0s
XS-GEM5 - Test new simulation script on RV64GCB
8m 13s
XS-GEM5 - Test new simulation script on RV64GCBV
6m 12s
XS-GEM5 - Test Multi-core + RV64GCB
6m 57s
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