arch-riscv: default disable vs bit, set misa with B-ext, update ref-so #26
Triggered via pull request
August 20, 2024 07:26
Status
Cancelled
Total duration
1h 1m 27s
Artifacts
–
gem5.yml
on: pull_request
XS-GEM5 - Running test checkpoints
43m 38s
XS-GEM5 - Check memory corruption
11m 56s
XS-GEM5 - Test new simulation script on RV64GCB
17m 26s
XS-GEM5 - Test new simulation script on RV64GCBV
15m 46s
XS-GEM5 - Test Multi-core + RV64GCB
8m 21s
Annotations
4 errors and 8 warnings