WIP: Create a backwards compatible flow for xo/xclbin generation with Calyx-AXI-wrapper
#2267
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…control of a component
TODO: Hook up the slices in the highest level module for ap_done, ap_start. Also thinnk about go done signals/how these connect to rest of wrapper
* Prepare fifo for case idiom * Attempt with . Failing due to empty control * Delete calyx-py/test/correctness/queues/fifo.futil
TODO: Hook up ap_start from controller in wrapper to the main_compute module
This works around #2198 causing combinational loops
…ess bases in axi_test.py
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The WIP [PR that tries to get an `yxi` powered end to end xilinx tools workflow up and running](#2267) ballooned into a beast and has gotten pretty stale. This is me trying to break things down into parts and slowly get everything merged. This changes the `*axi_generator.py` files to use underscores, which is needed for proper importing afaict. Also snuck in formatting changes to `dynamic_axi_generator.py`. These are pretty minor changes so going to merge when tests pass.
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Another part of #2267 that makes sense to live on it's own. Sorry for so many small PRs! But whittling things down like this is helping me better remember where everything stands
…og wrapper backwards compatability (i.e in gen_xo.tcl)
…patable with the new calyx-axi-wrapper and old verilog-axi-wrapper
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Another PR whittling down the changes present in #2267. This PR changes the toplevel clock signal from `clk` to `ap_clk`. This should allow us to reuse the existing [`gen_xo.tcl`](https://github.com/calyxir/calyx/blob/main/fud2/rsrc/gen_xo.tcl#L34-L37) and maintain backwards compatibility with the old verilog-axi-wrapper, without requiring a distinction between the two in the `gen_xo.tcl` file. Also fixes a bsd vs gnu `sed` syntax error. The new command should work on both. (bsd sed require terminating commands to end with a `;`, gnu does not) I'll also note that this PR touches a bunch of runt cocotb tests in `tests/axi`. I'm aware that there is a desire to get rid of large snapshots as they tend to get ignored. For now this setup is the best thing I have to make sure breaking changes aren't introduced to either axi-wrapper, so choosing to update them for now.
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This pull request has not seen activity in 14 days and is being marked as stale. If you're continuing work on this, please reply and state how to get this PR in a mergeable state or what issues it is blocked on. If the PR is not ready for review, please mark it as a draft. The PR will be closed in 7 days if there is no further activity. |
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@nathanielnrn are you planning to continue working on this? If so, let's break it up into mergeable pieces and upstream them! |
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At the highest level this PR should allow for correct
xclbins to be produced from Calyx programs.Broadly speaking this PR does 2 things (sorry for combining them, but some small fixes are sprinkled throughout making things hard to separate into their own changes):
axi_controller_generator.pywhich is meant to create a subordinate adhering to Xilinx's control spec. There might be some issues with this as executing on hardwares seems to hang at the moment, and the only difference between the generated verilog is the addition of the controller subordinate AFAIK..xo. This is different from the previous.futilto.xo(which should eventually be deprecated), and is the "correct" way to create a.xowith the new Calyx-AXI-wrappers.I'll do my best to comment the PR heavily to explain which changes affect what.
Furthermore, not sure if the controller itself needs a deep dive w.r.t code review. There are probably problems with it, that require waveform debugging to uncover.
EDIT: More work than I thought regarding backwards compatibility. Commented where changes are needed
In general there are a few outstanding TODOs even after this PR is merged. I'll make issues about these:
axi-generator.pytoaxi_generator.py| [fud2] AXI wrapper script cleanup & unified python names #2384