279 trademark policy process and checklist

[JohnTraverAmd]

Reviewed Process and Checklist Documents

[JohnTraverAmd]

I need to add the Trademark Images

[syncsrc-nv]

A few comments:

• I thought we'd agreed the External Entity Interaction Checklist Item could be dropped due to being redundant with the PA_USER requirement? Same for the Secure Mailbox Access checklist item.
• There is a note in the google docs version that the SRAM Zeroization Process item would be removed
• The Key Revoke Bits checklist item seems redundant given the Field-programmable requirement preceding it.
• The Debugging Controls checklist item needs to clarify what sensitive information needs to be protected, as Caliptra already takes the responsibility to protect its internal assets.
• The requirement for Log Functionality in SoC needs to clarify SOC versus Caliptra responsibility for providing tamper evidence.
• The Interface Wires section needs to define what "correctly implemented" means for the various signals.
• The Testing and Verification section is too broad to be a MUST requirement.

[Nitsirks]

{#introduction} displays in the preview.

[Nitsirks]

Should be field entropy here.

[steven-bellock]

Suggested change

The Caliptra Specification is maintained within the [ChipsAlliance Caliptra github](https://github.com/chipsalliance/Caliptra/blob/main/doc/Caliptra.md). This is a live link. Each generation, the main specification will be updated and the older specifications will be maintained for reference for designs based on that specification. For example, here is the specification for [Calitpra 1.X](https://github.com/chipsalliance/Caliptra/blob/main/doc/caliptra_1x/Caliptra.md).

The Caliptra Specification is maintained within the [ChipsAlliance Caliptra repository](https://github.com/chipsalliance/Caliptra/blob/main/doc/Caliptra.md). This is a live link. Each generation, the main specification will be updated and the older specifications will be maintained for reference for designs based on that specification. For example, here is the specification for [Calitpra 1.X](https://github.com/chipsalliance/Caliptra/blob/main/doc/caliptra_1x/Caliptra.md).

[steven-bellock]

Suggested change

	* **Requirement:** The confidentiality and integrity of the UDS seed and must be protected during generation, storage, and provisioning. Access to these assets must be strictly controlled, and any temporary storage must be securely zeroized after use.
	* **Requirement:** The confidentiality and integrity of the UDS seed must be protected during generation, storage, and provisioning. Access to this asset must be strictly controlled, and any temporary storage must be securely zeroized after use.

[steven-bellock]

In "generation, storage, and provisioning." storage refers to off-chip storage, on-chip storage (fuses), or both?

[steven-bellock]

There are EDA tools that will analyze the flow of confidential data and produce a report. For example https://eda.sw.siemens.com/en-US/ic/questa/formal-verification/secure-check/. Analysis at the RTL level is helpful at first, but the final analysis needs to be performed after synthesis and scan-cell insertion.

[steven-bellock]

Shouldn't this be the other way around, for when a security issue is found in Caliptra? If a flaw is found in Caliptra then presumably the Integrator needs a way to be alerted and hopefully open to deploying the fix if they can.