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Add width and binary point to fixed point names #555
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@shunshou mentioned in ucb-bar/dsptools#94 that it can be tricky to debug a circuit with fixed point signals in a verilog simulator.
Ideally, there would be some way to communicate to the waveform viewer that a particular signal is fixed point with a certain binary point, but support for this seems to be very lacking. GTKWave has a very barebones ability to set a binary point, but I don't see a way to use it programmatically. It doesn't look like simvision has any support for this. I'm not sure about DVE.
One idea is to embed the binary point information in the names of variables in the emitted verilog. For example "node x" might become "node x_q3", where q3 means binaryPoint=3. The q is in reference to this common way of writing fixed point numbers.
Having the binary point information embedded in the name prevents you from having to look between waveform outputs and firrtl to figure out what the binary point is supposed to be (in some cases it may be inferred, so you'll have the added annoyance of needing to run firrtl on your firrtl another time).
As written, this code is doing some dumb things. One obvious one to me is that it will rename port names on blackboxes- it shouldn't do that. I'm not really sure how to special case that out. I'm also not sure what signals get added by firrtl after this pass is run and if it is worth trying to add _qXXX suffixes to them too. I'm sure there are other consequences I'm not thinking of.
@shunshou @chick @azidar what do you think?