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WIP: add initial support for BELs chains #69

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kowalewskijan
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This is an initial version of BELs chains support. This is related to SymbiFlow/nextpnr#262
The main target for now is to get carry chains support for xilinx architectures, but the solution should be applicable for any architecture in the end. The PR includes what type of data we should pass to nextpnr in order to get the placement done of the BELs chains.

Signed-off-by: Jan Kowalewski [email protected]

litghost and others added 30 commits February 4, 2021 11:48
Signed-off-by: Keith Rothman <[email protected]>
Transferring from Xilinx/RapidWright
Signed-off-by: Keith Rothman <[email protected]>
Signed-off-by: Keith Rothman <[email protected]>
…_files

Add CMake file to build static library.
Signed-off-by: Keith Rothman <[email protected]>
…_build

Enable out of source build directory.
Add missing constant information to device database.
Add INIT parameter field and add comments to LUT section.
Signed-off-by: Keith Rothman <[email protected]>
Add entries for default parameters, and how to present parameters as strings.
Add DeviceResources to cxx_static Makefile and C++ namespace.
litghost and others added 25 commits March 29, 2021 17:31
Fields in capnproto shouldn't be deleted for backwards compability
reasons.

Signed-off-by: Keith Rothman <[email protected]>
Fix examples for format definitions, and add tombstone.
Signed-off-by: Keith Rothman <[email protected]>
- Some spelling and grammar fixes
- Added a section on control signals

Signed-off-by: Keith Rothman <[email protected]>
Signed-off-by: Keith Rothman <[email protected]>
…sign

Initial BEL and site design discussion.
…pping

Add note about cell to BEL mapping assumption.
Add discussion of the EOS S3 BEL and cell library.
Adding Sphinx documentation generation for the docs.
Signed-off-by: Tim 'mithro' Ansell <[email protected]>
This adds structures for DeviceResources for the default values for cell
pins that are missing or disconnected.

Previously the contract was that the synthesis tool would always give
cell pins a value, but this has several problems:

 - existing flows aren't doing this
 - cells might want to be created by the PnR tool or anything else
   reading the interchange format
 - sometimes, floating is a valid default value (for example certain
   dedicated pins) and the existing contract didn't recognise that
 - setting all disconnected pins to ground is definitely not correct,
   vendor tools usually connect disconnected clock enables to Vcc for
   example.

Signed-off-by: gatecat <[email protected]>
Add specification of default cell pin values
Signed-off-by: Jan Kowalewski <[email protected]>
@kowalewskijan kowalewskijan deleted the bels-chains-support branch April 26, 2021 16:19
@kowalewskijan kowalewskijan restored the bels-chains-support branch April 26, 2021 16:19
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6 participants