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fix issue with imm value for 64 bit instr
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Signed-off-by: aneels3 <[email protected]>
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aneels3 committed Jan 3, 2022
1 parent 3710b97 commit a8c65bf
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Showing 5 changed files with 58 additions and 9 deletions.
5 changes: 3 additions & 2 deletions pygen/pygen_src/isa/riscv_instr.py
Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,7 @@ def __init__(self):
self.has_rd = 1
self.has_imm = 1
self.shift_t = vsc.uint32_t(0xffffffff)
self.mask = 32
self.XLEN = vsc.uint32_t(32) # XLEN is used in constraint throughout the generator.
# Hence, XLEN should be of PyVSC type in order to use it in a constraint block
self.XLEN = rcs.XLEN
Expand Down Expand Up @@ -525,8 +526,8 @@ def update_imm_str(self):
self.imm_str = str(self.uintToInt(self.imm))

def uintToInt(self, x):
if x < (2 ** rcs.XLEN) / 2:
if x < (2 ** self.mask) / 2:
signed_x = x
else:
signed_x = x - 2 ** rcs.XLEN
signed_x = x - 2 ** self.mask
return signed_x
34 changes: 30 additions & 4 deletions pygen/pygen_src/isa/rv64c_instr.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,33 @@
from pygen_src.riscv_defines import DEFINE_INSTR
"""
Copyright 2020 Google LLC
Copyright 2020 PerfectVIPs Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
"""

from pygen_src.riscv_defines import DEFINE_C_INSTR
from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t,
riscv_instr_category_t, riscv_instr_group_t, imm_t)
riscv_instr_category_t, riscv_instr_group_t)


DEFINE_INSTR(riscv_instr_name_t.C_ADDIW, riscv_instr_format_t.CI_FORMAT,
riscv_instr_category_t.LOAD, riscv_instr_group_t.RV64C, g=globals())
DEFINE_C_INSTR(riscv_instr_name_t.C_ADDIW, riscv_instr_format_t.CI_FORMAT,
riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64C, g=globals())
DEFINE_C_INSTR(riscv_instr_name_t.C_SUBW, riscv_instr_format_t.CA_FORMAT,
riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64C, g=globals())
DEFINE_C_INSTR(riscv_instr_name_t.C_ADDW, riscv_instr_format_t.CA_FORMAT,
riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64C, g=globals())
DEFINE_C_INSTR(riscv_instr_name_t.C_LD, riscv_instr_format_t.CL_FORMAT,
riscv_instr_category_t.LOAD, riscv_instr_group_t.RV64C, g=globals())
DEFINE_C_INSTR(riscv_instr_name_t.C_SD, riscv_instr_format_t.CS_FORMAT,
riscv_instr_category_t.STORE, riscv_instr_group_t.RV64C, g=globals())
DEFINE_C_INSTR(riscv_instr_name_t.C_LDSP, riscv_instr_format_t.CI_FORMAT,
riscv_instr_category_t.LOAD, riscv_instr_group_t.RV64C, g=globals())
DEFINE_C_INSTR(riscv_instr_name_t.C_SDSP, riscv_instr_format_t.CSS_FORMAT,
riscv_instr_category_t.STORE, riscv_instr_group_t.RV64C, g=globals())
2 changes: 1 addition & 1 deletion pygen/pygen_src/isa/rv64i_instr.py
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@

from pygen_src.riscv_defines import DEFINE_INSTR
from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t,
riscv_instr_category_t, riscv_instr_group_t, imm_t)
riscv_instr_category_t, riscv_instr_group_t)


DEFINE_INSTR(riscv_instr_name_t.LWU, riscv_instr_format_t.I_FORMAT,
Expand Down
25 changes: 23 additions & 2 deletions pygen/pygen_src/isa/rv64m_instr.py
Original file line number Diff line number Diff line change
@@ -1,8 +1,29 @@
"""
Copyright 2020 Google LLC
Copyright 2020 PerfectVIPs Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
"""

from pygen_src.riscv_defines import DEFINE_INSTR
from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t,
riscv_instr_category_t, riscv_instr_group_t, imm_t)
riscv_instr_category_t, riscv_instr_group_t)


DEFINE_INSTR(riscv_instr_name_t.MULW, riscv_instr_format_t.R_FORMAT,
riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals())

DEFINE_INSTR(riscv_instr_name_t.DIVW, riscv_instr_format_t.R_FORMAT,
riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals())
DEFINE_INSTR(riscv_instr_name_t.DIVUW, riscv_instr_format_t.R_FORMAT,
riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals())
DEFINE_INSTR(riscv_instr_name_t.REMW, riscv_instr_format_t.R_FORMAT,
riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals())
DEFINE_INSTR(riscv_instr_name_t.REMUW, riscv_instr_format_t.R_FORMAT,
riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals())
1 change: 1 addition & 0 deletions pygen/pygen_src/target/rv64imc/riscv_core_setting.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
"""
Copyright 2020 Google LLC
Copyright 2020 PerfectVIPs Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
Expand Down

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