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Build(deps): Bump third_party/yosys from 6f3376c to fc88ea3 #6134

Build(deps): Bump third_party/yosys from 6f3376c to fc88ea3

Build(deps): Bump third_party/yosys from 6f3376c to fc88ea3 #6134

Triggered via pull request February 10, 2025 07:37
Status Failure
Total duration 30m 31s
Artifacts 4

main.yml

on: pull_request
Matrix: build-binaries
Emit Workflow Info
0s
Emit Workflow Info
Style check
2m 9s
Style check
Verify README Correctness (Installation From Sources)
30m 21s
Verify README Correctness (Installation From Sources)
Matrix: Large Designs Tests / opentitan_parse_report
Waiting for pending jobs
Matrix: Parsing Tests / parsing-tests
Waiting for pending jobs
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) with PySynlig)
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
Large Designs Tests / Black Parrot (ASIC synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Ibex (Vivado synthesis)
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Opentitan (synthesis)
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
Large Designs Tests / VeeR-EH1 (synthesis)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Waiting for pending jobs
Parsing Tests  /  Generate AST diff
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
Parsing Tests / Summary Generation
Release Package
0s
Release Package
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
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9 errors
Build Synlig Release
Process completed with exit code 2.
Build Package
Process completed with exit code 2.
Build Synlig (ASAN)
The job was canceled because "Build_Synlig_Release_bina" failed.
Build Synlig (ASAN)
The operation was canceled.
Build Plugin
The job was canceled because "Build_Synlig_Release_bina" failed.
Build Plugin
The operation was canceled.
Build PySynlig
The job was canceled because "Build_Synlig_Release_bina" failed.
Build PySynlig
The operation was canceled.
Verify README Correctness (Installation From Sources)
Process completed with exit code 2.

Artifacts

Produced during runtime
Name Size
plots_binaries-package
118 KB
plots_binaries-release
118 KB
plots_build_tools
77 KB
tools
39.2 MB