Build(deps): Bump third_party/black_parrot from 65c7db6
to 70d33a1
#6135
Triggered via pull request
February 11, 2025 07:11
Status
Failure
Total duration
1h 11m 59s
Artifacts
47
main.yml
on: pull_request
Matrix: build-binaries
Build tools
10m 40s
Emit Workflow Info
0s
Style check
1m 50s
Verify README Correctness (Installation From Sources)
43m 31s
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 20s
Large Designs Tests
/
Ibex (F4PGA synthesis)
11m 46s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
33m 17s
Large Designs Tests
/
Opentitan (synthesis)
50m 56s
Large Designs Tests
/
VeeR-EH1 (synthesis)
5m 32s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
3m 0s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
3m 45s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) with PySynlig)
4m 13s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
6m 37s
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests
/
Generate AST diff
1m 46s
Parsing Tests
/
Summary Generation
1m 49s
Verify README Correctness (Download And Run Release)
0s
Annotations
3 errors and 3 warnings
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Process completed with exit code 2.
|
Large Designs Tests / Black Parrot (ASIC synthesis)
Process completed with exit code 2.
|
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Process completed with exit code 2.
|
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
|
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
|
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
|
Artifacts
Produced during runtime
Name | Size | |
---|---|---|
binaries-asan
|
292 MB |
|
binaries-package
|
23.2 MB |
|
binaries-plugin
|
41.7 MB |
|
binaries-pysynlig
|
651 MB |
|
binaries-release
|
42 MB |
|
bsg-logs
|
5.57 MB |
|
bsg-outputs
|
1.73 MB |
|
formal-verification-logs-simple
|
18.4 MB |
|
formal-verification-logs-sv2v
|
62.7 MB |
|
formal-verification-logs-yosys
|
50.2 MB |
|
lowrisc_ibex_top_artya7_surelog_0.1.bit
|
105 KB |
|
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
|
616 KB |
|
opentitan-logs-full
|
4.59 MB |
|
opentitan-logs-quick
|
827 KB |
|
plots_binaries-asan
|
123 KB |
|
plots_binaries-package
|
126 KB |
|
plots_binaries-plugin
|
127 KB |
|
plots_binaries-pysynlig
|
145 KB |
|
plots_binaries-release
|
126 KB |
|
plots_blackparrot_synth_asic
|
27.2 KB |
|
plots_blackparrot_synth_xilinx
|
21.9 KB |
|
plots_blackparrot_synth_xilinx_python
|
29.2 KB |
|
plots_build_tools
|
78.5 KB |
|
plots_formal_verification_simple
|
114 KB |
|
plots_formal_verification_sv2v
|
118 KB |
|
plots_formal_verification_yosys
|
100 KB |
|
plots_ibex_synth
|
45.5 KB |
|
plots_ibex_synth_f4pga
|
81.5 KB |
|
plots_opentitan_9d82960888_synth
|
189 KB |
|
plots_opentitan_parse_report_full
|
87.6 KB |
|
plots_opentitan_parse_report_quick
|
39 KB |
|
plots_opentitan_synth
|
286 KB |
|
plots_tests_asan_read_systemverilog
|
225 KB |
|
plots_tests_asan_read_uhdm
|
168 KB |
|
plots_tests_plugin_read_systemverilog
|
36.8 KB |
|
plots_tests_plugin_read_uhdm
|
33.4 KB |
|
plots_tests_release_read_systemverilog
|
34.9 KB |
|
plots_tests_release_read_uhdm
|
33.8 KB |
|
plots_veer_synth
|
39.3 KB |
|
results_parsing_tests_asan_read_systemverilog
Expired
|
1.6 MB |
|
results_parsing_tests_asan_read_uhdm
Expired
|
1.81 MB |
|
results_parsing_tests_plugin_read_systemverilog
Expired
|
1.53 MB |
|
results_parsing_tests_plugin_read_uhdm
Expired
|
1.78 MB |
|
results_parsing_tests_release_read_systemverilog
Expired
|
1.48 MB |
|
results_parsing_tests_release_read_uhdm
Expired
|
1.73 MB |
|
tools
|
39.2 MB |
|
top_artya7.bit
|
119 KB |
|