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T1Emu Verilator Daily Regression #51

T1Emu Verilator Daily Regression

T1Emu Verilator Daily Regression #51

Triggered via schedule September 6, 2024 22:33
Status Failure
Total duration 14m 20s
Artifacts

verilator.yml

on: schedule
Generate test plan
8s
Generate test plan
Matrix: Build Verilator Emulators
Matrix: Build verilator trace emulators
Prepare for running testcases
8s
Prepare for running testcases
Matrix: Run testcases
Report CI result
0s
Report CI result
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74 errors
Build verilator trace emulators (blastoise)
Process completed with exit code 1.
Build verilator trace emulators (psyduck)
Process completed with exit code 1.
Build verilator trace emulators (machamp)
Process completed with exit code 1.
Run testcases (blastoise,pytorch.mobilenet, 1)
Process completed with exit code 1.
Run testcases (sandslash,codegen.vslide1up_vx, 4)
Process completed with exit code 1.
Run testcases (sandslash,codegen.vslidedown_vx, 3)
Process completed with exit code 1.
Run testcases (sandslash,codegen.vslidedown_vi, 6)
Process completed with exit code 1.
Run testcases (sandslash,codegen.vslideup_vx, 5)
Process completed with exit code 1.
Run testcases (sandslash,codegen.vslide1down_vx, 2)
Process completed with exit code 1.
Run testcases (sandslash,codegen.vslideup_vi, 7)
Process completed with exit code 1.
Build verilator trace emulators (sandslash)
Process completed with exit code 1.