[rtl] fix reduce result

chipsalliance · Nov 9, 2024 · 1dd9602 · 1dd9602
1 parent aca05e4
commit 1dd9602
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1/src/mask/MaskReduce.scala b/t1/src/mask/MaskReduce.scala
@@ -195,6 +195,6 @@ class MaskReduce(parameter: T1Parameter) extends Module {
   )
 
   out.valid     := outValid
-  out.bits.data := reduceResult
+  out.bits.data := Mux(updateResult, reduceResult, reduceInit)
   out.bits.mask := writeMask & Fill(4, validInst)
 }