fix early end of t1rocketemu

difftest/dpi_t1emu/src/dpi.rs

@@ -87,10 +87,6 @@ pub static ISSUE_VALID: u32 = 1;
 pub static ISSUE_FENCE: u32 = 2;
 pub static ISSUE_EXIT: u32 = 3;
 
-pub static WATCHDOG_CONTINUE: u8 = 0;
-pub static WATCHDOG_TIMEOUT: u8 = 1;
-pub static WATCHDOG_QUIT: u8 = 255;
-
 #[repr(C, packed)]
 pub(crate) struct Retire {
   pub vxsat: u32,
@@ -245,6 +241,13 @@ unsafe extern "C" fn t1_cosim_watchdog() -> u8 {
   TARGET.with(|driver| driver.watchdog())
 }
 
+#[no_mangle]
+unsafe extern "C" fn t1_cosim_refresh() {
+  TARGET.with(|driver| {
+    driver.last_commit_cycle = crate::get_t();
+  })
+}
+
 /// evaluate at instruction queue is not empty
 /// arg issue will be type cast from a struct to svBitVecVal*(uint32_t*)
 #[no_mangle]

difftest/dpi_t1emu/src/drive.rs

@@ -105,10 +105,10 @@ pub(crate) struct Driver {
 
   pub(crate) dlen: u32,
 
-  timeout: u64,
+  max_commit_interval: u64,
 
   // driver state
-  last_commit_cycle: u64,
+  pub(crate) last_commit_cycle: u64,
   issued: u64,
   vector_lsu_count: u8,
 
@@ -134,7 +134,7 @@ impl Driver {
       success: false,
 
       dlen: args.dlen,
-      timeout: args.timeout,
+      max_commit_interval: args.max_commit_interval,
       last_commit_cycle: 0,
 
       issued: 0,
@@ -204,16 +204,20 @@ impl Driver {
   }
 
   pub(crate) fn watchdog(&mut self) -> u8 {
+    const WATCHDOG_CONTINUE: u8 = 0;
+    const WATCHDOG_TIMEOUT: u8 = 1;
+    const WATCHDOG_QUIT: u8 = 255;
+
     let tick = get_t();
 
     if self.success {
       trace!("[{tick}] watchdog quit");
       return WATCHDOG_QUIT;
     }
 
-    if tick - self.last_commit_cycle > self.timeout {
+    if tick - self.last_commit_cycle > self.max_commit_interval {
       error!(
-        "[{tick}] watchdog timeout (last_commit_cycle={})",
+        "[{tick}] watchdog timeout since last commit (last_commit_cycle={})",
         self.last_commit_cycle
       );
       return WATCHDOG_TIMEOUT;
@@ -321,6 +325,7 @@ impl Driver {
     self.shadow_mem.apply_writes(&se.mem_access_record);
 
     self.spike_runner.commit_queue.pop_back();
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
   }
 

difftest/dpi_t1emu/src/lib.rs

@@ -21,25 +21,29 @@ pub(crate) struct OnlineArgs {
   /// ISA config
   pub set: String,
 
-  // default to TIMEOUT_DEFAULT
-  pub timeout: u64,
+  // default to max_commit_interval * vlen / dlen
+  pub max_commit_interval: u64,
 }
 
-const TIMEOUT_DEFAULT: u64 = 100000000;
+const MAX_COMMIT_INTERVAL_COEFFICIENT: u64 = 10_0000;
 
 impl OnlineArgs {
   pub fn from_plusargs(matcher: &PlusArgMatcher) -> Self {
+    let vlen = env!("DESIGN_VLEN").parse().unwrap();
+    let dlen = env!("DESIGN_DLEN").parse().unwrap();
+    let max_commit_interval_coefficient = matcher
+      .try_match("t1_max_commit_interval_coefficient")
+      .map(|x| x.parse().unwrap())
+      .unwrap_or(MAX_COMMIT_INTERVAL_COEFFICIENT);
+    let max_commit_interval = max_commit_interval_coefficient * ((vlen / dlen) as u64);
+
     Self {
       elf_file: matcher.match_("t1_elf_file").into(),
       log_file: matcher.try_match("t1_log_file").map(|x| x.into()),
-
-      vlen: env!("DESIGN_VLEN").parse().unwrap(),
-      dlen: env!("DESIGN_DLEN").parse().unwrap(),
+      vlen,
+      dlen,
       set: env!("SPIKE_ISA_STRING").parse().unwrap(),
-      timeout: matcher
-        .try_match("t1_timeout")
-        .map(|x| x.parse().unwrap())
-        .unwrap_or(TIMEOUT_DEFAULT),
+      max_commit_interval,
     }
   }
 }

difftest/dpi_t1rocketemu/src/dpi.rs

@@ -313,6 +313,14 @@ unsafe extern "C" fn t1_cosim_watchdog() -> u8 {
   TARGET.with(|driver| driver.watchdog())
 }
 
+/// update last_commit_cycle to current cycle
+#[no_mangle]
+unsafe extern "C" fn t1_cosim_refresh() {
+  TARGET.with(|driver| {
+    driver.last_commit_cycle = crate::get_t();
+  })
+}
+
 #[no_mangle]
 unsafe extern "C" fn get_resetvector(resetvector: *mut c_longlong) {
   TARGET.with_optional(|driver| {

difftest/dpi_t1rocketemu/src/drive.rs

@@ -32,8 +32,8 @@ pub(crate) struct Driver {
   pub(crate) dlen: u32,
   pub(crate) e_entry: u64,
 
-  timeout: u64,
-  last_commit_cycle: u64,
+  max_commit_interval: u64,
+  pub(crate) last_commit_cycle: u64,
 
   shadow_bus: ShadowBus,
 
@@ -53,7 +53,7 @@ impl Driver {
       dlen: args.dlen,
       e_entry,
 
-      timeout: args.timeout,
+      max_commit_interval: args.max_commit_interval,
       last_commit_cycle: 0,
 
       shadow_bus,
@@ -134,6 +134,7 @@ impl Driver {
     let size = 1 << arsize;
     let data = self.shadow_bus.read_mem_axi(addr, size, self.dlen / 8);
     let data_hex = hex::encode(&data);
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
     trace!(
       "[{}] axi_read_high_bandwidth (addr={addr:#x}, size={size}, data={data_hex})",
@@ -152,6 +153,7 @@ impl Driver {
     let size = 1 << awsize;
     self.shadow_bus.write_mem_axi(addr, size, self.dlen / 8, &strobe, data);
     let data_hex = hex::encode(data);
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
     trace!(
       "[{}] axi_write_high_bandwidth (addr={addr:#x}, size={size}, data={data_hex})",
@@ -164,6 +166,7 @@ impl Driver {
     assert!(size <= 4);
     let data = self.shadow_bus.read_mem_axi(addr, size, 4);
     let data_hex = hex::encode(&data);
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
     trace!(
       "[{}] axi_read_high_outstanding (addr={addr:#x}, size={size}, data={data_hex})",
@@ -182,6 +185,7 @@ impl Driver {
     let size = 1 << awsize;
     self.shadow_bus.write_mem_axi(addr, size, 4, strobe, data);
     let data_hex = hex::encode(data);
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
     trace!(
       "[{}] axi_write_high_outstanding (addr={addr:#x}, size={size}, data={data_hex})",
@@ -194,6 +198,7 @@ impl Driver {
     let bus_size = if size == 32 { 32 } else { 4 };
     let data = self.shadow_bus.read_mem_axi(addr, size, bus_size);
     let data_hex = hex::encode(&data);
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
     trace!(
       "[{}] axi_read_load_store (addr={addr:#x}, size={size}, data={data_hex})",
@@ -213,6 +218,7 @@ impl Driver {
     let bus_size = if size == 32 { 32 } else { 4 };
     self.shadow_bus.write_mem_axi(addr, size, bus_size, strobe, data);
     let data_hex = hex::encode(data);
+    // TODO: use t1_cosim_refresh instead
     self.last_commit_cycle = get_t();
 
     trace!(
@@ -254,9 +260,9 @@ impl Driver {
       return WATCHDOG_QUIT;
     }
 
-    if tick - self.last_commit_cycle > self.timeout {
+    if tick - self.last_commit_cycle > self.max_commit_interval {
       error!(
-        "[{tick}] watchdog timeout (last_commit_cycle={})",
+        "[{tick}] watchdog timeout since last commit (last_commit_cycle={})",
         self.last_commit_cycle
       );
       return WATCHDOG_TIMEOUT;

difftest/dpi_t1rocketemu/src/lib.rs

@@ -13,21 +13,24 @@ pub(crate) struct OnlineArgs {
   /// dlen config
   pub dlen: u32,
 
-  // default to TIMEOUT_DEFAULT
-  pub timeout: u64,
+  // default to max_commit_interval
+  pub max_commit_interval: u64,
 }
 
-const TIMEOUT_DEFAULT: u64 = 100000000;
+const MAX_COMMIT_INTERVAL_COEFFICIENT: u64 = 10_0000;
 
 impl OnlineArgs {
   pub fn from_plusargs(matcher: &PlusArgMatcher) -> Self {
+    let max_commit_interval_coefficient = matcher
+      .try_match("t1_max_commit_interval_coefficient")
+      .map(|x| x.parse().unwrap())
+      .unwrap_or(MAX_COMMIT_INTERVAL_COEFFICIENT);
+    let max_commit_interval = max_commit_interval_coefficient;
+
     Self {
       elf_file: matcher.match_("t1_elf_file").into(),
       dlen: env!("DESIGN_DLEN").parse().unwrap(),
-      timeout: matcher
-        .try_match("t1_timeout")
-        .map(|x| x.parse().unwrap())
-        .unwrap_or(TIMEOUT_DEFAULT),
+      max_commit_interval,
     }
   }
 }

difftest/offline_t1emu/src/difftest.rs

@@ -25,19 +25,14 @@ impl Difftest {
     let event = self.dut.step()?;
 
     match event {
-      JsonEvents::SimulationStart { cycle } => {
-        self.runner.cycle = *cycle;
-        Ok(())
-      }
+      JsonEvents::SimulationStart { cycle } => Ok(()),
       JsonEvents::SimulationStop { reason, cycle } => {
         anyhow::bail!("stop: simulation stopped at cycle {cycle}, reason {reason}")
       }
       JsonEvents::Issue { idx, cycle } => {
-        self.runner.cycle = *cycle;
         self.runner.peek_issue(&IssueEvent { idx: *idx, cycle: *cycle })
       }
       JsonEvents::MemoryWrite { mask, data, lsu_idx, address, cycle } => {
-        self.runner.cycle = *cycle;
         self.runner.peek_memory_write(&MemoryWriteEvent {
           mask: mask.clone(),
           data: data.clone(),
@@ -47,11 +42,9 @@ impl Difftest {
         })
       }
       JsonEvents::LsuEnq { enq, cycle } => {
-        self.runner.cycle = *cycle;
         self.runner.update_lsu_idx(&LsuEnqEvent { enq: *enq, cycle: *cycle })
       }
       JsonEvents::VrfWrite { issue_idx, vd, offset, mask, data, lane, cycle } => {
-        self.runner.cycle = *cycle;
         self.runner.peek_vrf_write(&VrfWriteEvent {
           issue_idx: *issue_idx,
           vd: *vd,
@@ -63,12 +56,10 @@ impl Difftest {
         })
       }
       JsonEvents::CheckRd { data, issue_idx, cycle } => {
-        self.runner.cycle = *cycle;
         self.runner.check_rd(&CheckRdEvent { data: *data, issue_idx: *issue_idx, cycle: *cycle })
       }
-      JsonEvents::VrfScoreboardReport { count, issue_idx, cycle } => {
-        self.runner.cycle = *cycle;
-        self.runner.vrf_scoreboard_report(&VrfScoreboardReportEvent {
+      JsonEvents::VrfScoreboard { count, issue_idx, cycle } => {
+        self.runner.vrf_scoreboard(&VrfScoreboardEvent {
           count: *count,
           issue_idx: *issue_idx,
           cycle: *cycle,

difftest/offline_t1emu/src/json_events.rs

@@ -87,7 +87,7 @@ pub(crate) enum JsonEvents {
     issue_idx: u8,
     cycle: u64,
   },
-  VrfScoreboardReport {
+  VrfScoreboard {
     count: u32,
     issue_idx: u8,
     cycle: u64,
@@ -122,7 +122,7 @@ pub struct MemoryWriteEvent {
   pub cycle: u64,
 }
 
-pub struct VrfScoreboardReportEvent {
+pub struct VrfScoreboardEvent {
   pub count: u32,
   pub issue_idx: u8,
   pub cycle: u64,
@@ -141,7 +141,7 @@ pub(crate) trait JsonEventRunner {
 
   fn peek_vrf_write(&mut self, vrf_write: &VrfWriteEvent) -> anyhow::Result<()>;
 
-  fn vrf_scoreboard_report(&mut self, report: &VrfScoreboardReportEvent) -> anyhow::Result<()>;
+  fn vrf_scoreboard(&mut self, report: &VrfScoreboardEvent) -> anyhow::Result<()>;
 
   fn peek_memory_write(&mut self, memory_write: &MemoryWriteEvent) -> anyhow::Result<()>;
 
@@ -314,7 +314,7 @@ impl JsonEventRunner for SpikeRunner {
     panic!("[{cycle}] cannot find se with instruction lsu_idx={lsu_idx}")
   }
 
-  fn vrf_scoreboard_report(&mut self, report: &VrfScoreboardReportEvent) -> anyhow::Result<()> {
+  fn vrf_scoreboard(&mut self, report: &VrfScoreboardEvent) -> anyhow::Result<()> {
     let count = report.count;
     let issue_idx = report.issue_idx;
     let cycle = report.cycle;
@@ -336,7 +336,7 @@ impl JsonEventRunner for SpikeRunner {
       se.vrf_access_record.unretired_writes = Some(count - se.vrf_access_record.retired_writes);
 
       info!(
-        "[{cycle}] VrfScoreboardReport: count={count}, issue_idx={issue_idx}, retired={} ({})",
+        "[{cycle}] VrfScoreboard: count={count}, issue_idx={issue_idx}, retired={} ({})",
         se.vrf_access_record.retired_writes,
         se.describe_insn()
       );