Adding all ASAP7 standard cell libraries.

[mithro]

No description provided.

[mithro]

@QuantamHD - Does this direction make sense to you?

[QuantamHD]

Seems to make sense so far. You'll need to include the file groups in some kind of OpenROAD related rule, but it's definietly a good way to organize the files.

[QuantamHD]

Prefer using NLDM over CCS for OpenROAD. We don't have support for CCS yet so it's not adding a lot of value, but does consume a good bit of disk.

[QuantamHD]

Looks like one of the target names is off. '@org_theopenroadproject_asap7//:asap7_rvt_1x': target 'asap7_rvt_1x' not declared in package '' (did you mean 'asap7_rvt_tt'

[mithro]

@QuantamHD - Can you please take another look.

Now getting close to having rvt, lvt, slvt going for the rev 26, 27 & 28 cells.

[mithro]

The naming scheme I ended up with is <pdk>-(cells|srams)-<stdcell lib name>-<type>.

[mithro]

The rev28 version of verilog_counter seems to work for the rvt, lvt and slvt cell types -- //synthesis/tests:verilog_counter-asap7-sc7p5t_rev28_rvt-place_and_route <-- This target

[QuantamHD]

Let me know when this is ready.

[mithro]

Let me know when this is ready.

@QuantamHD - I'm working through making everything compile but would like you to review before that happens.

[mithro]

I have done a rebase based on the ASAP7 repo reorg now.

It actually makes a bunch of things a bit cleaner.

@QuantamHD - PTAL.

[QuantamHD]

Looking now

[QuantamHD]

LGTM! Looks really beautiful @mithro

[mithro]

Currently debugging;

//synthesis/tests:build-verilog_counter                         (cached) PASSED in 0.1s                                                                                                                           
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_lvt-synth (cached) PASSED in 0.1s                                                                                                                        
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_lvt-synth_sta (cached) PASSED in 0.1s                                                                                                                    
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_rvt-synth (cached) PASSED in 0.1s                                                                                                                        
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_rvt-synth_sta (cached) PASSED in 0.2s                                                                                                                    
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_slvt-synth (cached) PASSED in 0.1s                                                                                                                       
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_slvt-synth_sta (cached) PASSED in 0.1s                                                                                                                   
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_lvt-synth (cached) PASSED in 0.1s                                                                                                                      
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_lvt-synth_sta (cached) PASSED in 0.3s                                                                                                                  
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt-synth (cached) PASSED in 0.2s                                                                                                                      
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt-synth_sta (cached) PASSED in 0.2s                                                                                                                  
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth (cached) PASSED in 0.1s                                                                                                                   
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth_sta (cached) PASSED in 0.1s                                                                                                               
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_slvt-synth (cached) PASSED in 0.1s                                                                                                                     
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_slvt-synth_sta (cached) PASSED in 0.1s                                                                                                                 
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_lvt-synth (cached) PASSED in 0.1s                                                                                                                      
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_lvt-synth_sta (cached) PASSED in 0.1s                                                                                                                  
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_rvt-synth (cached) PASSED in 0.1s                                                                                                                      
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_rvt-synth_sta (cached) PASSED in 0.1s                                                                                                                  
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt-synth (cached) PASSED in 0.1s                                                                                                                     
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt-synth_sta (cached) PASSED in 0.1s                                                                                                                 
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_lvt-gds      NO STATUS                                                                                                                                   //synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_lvt-place_and_route NO STATUS                                                                                                                            //synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_rvt-gds      NO STATUS
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_rvt-place_and_route NO STATUS                
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_slvt-gds     NO STATUS                                                                                                                                   
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_slvt-place_and_route NO STATUS                                                                                                                           
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_lvt-gds    NO STATUS
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_lvt-place_and_route NO STATUS
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt-gds    NO STATUS                                                                                                                                   
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt-place_and_route NO STATUS                                                                                                                          
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt_4x-place_and_route NO STATUS                                                                                                                       
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_slvt-gds   NO STATUS                                                                                                                                   
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_slvt-place_and_route NO STATUS                                                                                                                         
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_lvt-gds    NO STATUS                                                                                                                                   
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_lvt-place_and_route NO STATUS                                                                                                                          
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_rvt-gds    NO STATUS                                                                                                                                   
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_rvt-place_and_route NO STATUS                                                                                                                          
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt-gds   NO STATUS                                                                                                                                   
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt-place_and_route NO STATUS       

[mithro]

INFO: Elapsed time: 120.709s, Critical Path: 120.15s                                                                                                                                                              
INFO: 11 processes: 11 internal.                                                                                                                                                                                  
FAILED: Build did NOT complete successfully                                                                                                                                                                       
//synthesis/tests:build-verilog_counter                         (cached) PASSED in 0.1s                                                                                                                           
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_lvt-synth (cached) PASSED in 0.1s                                                                                                                        
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_lvt-synth_sta (cached) PASSED in 0.1s                                                                                                                    
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_rvt-synth (cached) PASSED in 0.1s                                                                                                                        
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_rvt-synth_sta (cached) PASSED in 0.2s                                                                                                                    
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_slvt-synth (cached) PASSED in 0.1s                                                                                                                       
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_slvt-synth_sta (cached) PASSED in 0.1s                                                                                                                   
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_lvt-synth (cached) PASSED in 0.1s                                                                                                                      
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_lvt-synth_sta (cached) PASSED in 0.3s                                                                                                                  
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt-synth (cached) PASSED in 0.2s                                                                                                                      
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt-synth_sta (cached) PASSED in 0.2s                                                                                                                  
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth (cached) PASSED in 0.1s                                                                                                                   
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth_sta (cached) PASSED in 0.1s                                                                                                               
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_slvt-synth (cached) PASSED in 0.1s                                                                                                                     
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_slvt-synth_sta (cached) PASSED in 0.1s                                                                                                                 
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_lvt-synth (cached) PASSED in 0.1s             
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_lvt-synth_sta (cached) PASSED in 0.1s                                                                                                                  
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_rvt-synth (cached) PASSED in 0.1s                                                                                                                      
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_rvt-synth_sta (cached) PASSED in 0.1s                                                                                                                  //synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt-synth (cached) PASSED in 0.1s                                                                                                                     //synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt-synth_sta (cached) PASSED in 0.1s                                                                                                                 
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_lvt-gds FAILED TO BUILD
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_lvt-place_and_route FAILED TO BUILD                                                                                                                      
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_rvt-gds FAILED TO BUILD                                                                                                                                  
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_rvt-place_and_route FAILED TO BUILD
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_slvt-gds FAILED TO BUILD
(Skipping other failed to build tests)                                                                   
                                                    
Executed 0 out of 40 tests: 21 tests pass and 19 fail to build.                                                                   

[mithro]

Currently debugging a few small things;

[WARNING IFP-0028] Core area lower left (1.000, 1.000) snapped to (1.026, 1.080).
[ERROR IFP-0031] Unable to find master: TIEHIx1_ASAP7_75t_SL
Error: verilog_counter-asap7-sc6t_rev26_slvt-place_and_route__floorplan_script.tcl, 8 IFP-0031

[WARNING IFP-0028] Core area lower left (1.000, 1.000) snapped to (1.026, 1.080).
[ERROR IFP-0031] Unable to find master: TIEHIx1_ASAP7_75t_L
Error: verilog_counter-asap7-sc6t_rev26_lvt-place_and_route__floorplan_script.tcl, 8 IFP-0031

[mithro]

[WARNING STA-0164] bazel-out/k8-fastbuild/bin/external/org_theopenroadproject_asap7sc7p5t_27/asap7-sc7p5t_rev27_rvt_4x_SS.lib line 2858187, timing group from output port.
[ERROR GRT-0118] Routing congestion too high. Check the congestion heatmap in the GUI.
Error: verilog_counter-asap7-sc7p5t_rev27_rvt_4x-place_and_route__global_routing_script.tcl, 14 GRT-0118

[mithro]

ERROR: /ssd/github/mithro/bazel_rules_hdl/synthesis/tests/BUILD:123:14: OpenROAD synthesis/tests/verilog_counter-asap7-sc7p5t_rev27_lvt-place_and_route__pdn_generation.db failed: (Exit 1): openroad failed: erro
r executing command (from target //synthesis/tests:verilog_counter-asap7-sc7p5t_rev27_lvt-place_and_route) bazel-out/k8-opt-exec-2B5CBBC6/bin/external/org_theopenroadproject/openroad -no_init -no_splash -thread
s max -exit -log ... (remaining 3 arguments skipped)                                                                                                                                                              
                                                                                                                                                                                                                  
Use --sandbox_debug to see verbose messages from the sandbox and retain the sandbox build root for debugging                                                       
[WARNING ORD-0046] -defer_connection has been deprecated.                                                                                                                                                         
[WARNING ORD-0046] -defer_connection has been deprecated.                                                                                                                                                         
[WARNING ORD-0046] -defer_connection has been deprecated.                                                                                                                                                         
[WARNING ORD-0046] -defer_connection has been deprecated.                                                                                                                                                         
[WARNING ORD-0046] -defer_connection has been deprecated.                                                                                                                                                         
[ERROR PDN-0106] Width (0.0180 um) specified for layer M1 is less than minimum width (0.0720 um).                                                                                                                 
Error: pdn_config_1x.pdn, 32 PDN-0106                       

[mithro]

INFO: Elapsed time: 174.575s, Critical Path: 129.57s
INFO: 37 processes: 2 remote cache hit, 5 internal, 30 linux-sandbox.
FAILED: Build did NOT complete successfully
//cocotb/tests:cocotb_counter                                   (cached) PASSED in 0.7s
//dependency_support:pip_requirements_test                      (cached) PASSED in 6.1s
//dependency_support:test_vendored                              (cached) PASSED in 0.0s
//flows/tests:openroad_step_smoke                               (cached) PASSED in 0.1s
//flows/tests:synth_sky130_smoke                                (cached) PASSED in 0.1s
//pdk/liberty:cell_parser_test                                  (cached) PASSED in 0.3s
//pdk/liberty:liberty_utility_test                              (cached) PASSED in 0.3s
//synthesis/tests:build-verilog_counter                         (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_lvt-synth (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_lvt-synth_sta (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_rvt-synth (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_rvt-synth_sta (cached) PASSED in 0.2s
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_slvt-synth (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_slvt-synth_sta (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_lvt-synth (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_lvt-synth_sta (cached) PASSED in 0.3s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt-synth (cached) PASSED in 0.2s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt-synth_sta (cached) PASSED in 0.2s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth_sta (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_slvt-synth (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_slvt-synth_sta (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_lvt-gds (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_lvt-place_and_route (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_lvt-synth (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_lvt-synth_sta (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_rvt-gds (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_rvt-place_and_route (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_rvt-synth (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_rvt-synth_sta (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt-gds (cached) PASSED in 0.2s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt-place_and_route (cached) PASSED in 0.2s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt-synth (cached) PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev28_slvt-synth_sta (cached) PASSED in 0.1s
//verilator/tests:adder_test                                    (cached) PASSED in 0.1s
//verilator/tests:load_and_count_test                           (cached) PASSED in 0.1s
//verilator/tests:nested_module_test                            (cached) PASSED in 0.1s
//vivado/tests:johnson_counter_test                             (cached) PASSED in 0.3s
//vivado/tests:weights_replay_test                              (cached) PASSED in 0.6s
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_lvt-place_and_route FAILED TO BUILD
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_rvt-place_and_route FAILED TO BUILD
//synthesis/tests:build-verilog_counter-asap7-sc6t_rev26_slvt-place_and_route FAILED TO BUILD
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt_4x-place_and_route FAILED TO BUILD
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_lvt-place_and_route PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt-gds       PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_rvt-place_and_route PASSED in 0.1s
//synthesis/tests:build-verilog_counter-asap7-sc7p5t_rev27_slvt-place_and_route PASSED in 0.1s

Executed 4 out of 47 tests: 43 tests pass and 4 fail to build.
There were tests whose specified size is too big. Use the --test_verbose_timeout_warnings command line option to see which ones these are.