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    32 repositories

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •68•0•0•0•Updated Feb 28, 2025Feb 28, 2025

    • meta-cva6-yocto

      Public
      Yocto layer for CVA6
      Shell
      •
      MIT License
      •4•0•0•0•Updated Feb 27, 2025Feb 27, 2025

    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      C++
      •
      GNU Lesser General Public License v3.0
      •637•1•0•0•Updated Feb 26, 2025Feb 26, 2025

    • PlanV_Verilator_Feature_Tests

      Public
      PlanV CI System for testing Verilator-Features
      SystemVerilog
      •
      Other
      •0•1•0•0•Updated Feb 26, 2025Feb 26, 2025

    • cva6

      Public
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      Assembly
      •
      Other
      •735•3•0•0•Updated Feb 26, 2025Feb 26, 2025

    • u-boot

      Public
      Unofficial development fork of U-Boot
      C
      •12•0•0•0•Updated Feb 25, 2025Feb 25, 2025

    • core-v-verif

      Public
      Functional verification project for the CORE-V family of RISC-V cores.
      Assembly
      •
      Other
      •232•1•0•0•Updated Feb 24, 2025Feb 24, 2025

    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      •
      Other
      •547•0•0•0•Updated Feb 13, 2025Feb 13, 2025

    • SoC_Amaranth

      Public
      SoC integrated using Amaratnh HDL
      Verilog
      •0•0•0•0•Updated Nov 14, 2024Nov 14, 2024

    • ibex

      Public
      Buggy Ibex
      SystemVerilog
      •
      Apache License 2.0
      •585•0•0•0•Updated Oct 3, 2024Oct 3, 2024

    • cva6_axi_dma

      Public
      SystemVerilog
      •0•1•0•0•Updated Jul 4, 2024Jul 4, 2024

    • robo-v-mcu-demo

      Public
      C
      •
      Other
      •4•0•0•0•Updated Jun 24, 2024Jun 24, 2024

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •16•0•0•0•Updated Jun 10, 2024Jun 10, 2024

    • axi_mem_if

      Public
      Simple single-port AXI memory interface
      SystemVerilog
      •
      Other
      •25•0•0•0•Updated Jun 7, 2024Jun 7, 2024

    • axi_spi_slave

      Public
      SystemVerilog
      •
      Other
      •33•0•0•0•Updated May 21, 2024May 21, 2024

    • cva6-h

      Public
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      Assembly
      •
      Other
      •735•0•0•0•Updated Mar 20, 2024Mar 20, 2024

    • cva6-perf-model

      Public
      Python
      •
      Other
      •4•0•0•0•Updated Mar 14, 2024Mar 14, 2024

    • cva6_mmu_hyp

      Public
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      SystemVerilog
      •
      Other
      •735•0•0•0•Updated Mar 7, 2024Mar 7, 2024

    • apb_uart

      Public
      VHDL
      •24•0•0•0•Updated Mar 4, 2024Mar 4, 2024

    • cva6-litmus

      Public
      A tool to run litmus tests on bare-metal cva6
      C
      •
      Other
      •13•2•0•0•Updated Feb 28, 2024Feb 28, 2024

    • Splash-3

      Public
      The Splash-3 benchmark suite
      GLSL
      •28•0•0•0•Updated Dec 15, 2023Dec 15, 2023

    • apb_timer

      Public
      APB Timer Unit
      SystemVerilog
      •
      Other
      •22•0•0•0•Updated Nov 17, 2023Nov 17, 2023

    • core-v-mcu

      Public
      This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
      SystemVerilog
      •
      Other
      •57•0•0•0•Updated Oct 30, 2023Oct 30, 2023

    • cva6_pulp

      Public
      This is the fork of CVA6 intended for PULP development.
      SystemVerilog
      •
      Other
      •735•0•0•0•Updated Oct 30, 2023Oct 30, 2023

    • rv_plic

      Public
      Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC). DEPRECATED in favour of the OpenTitan PLIC: https://github.com/lowRISC/opentitan/tree/master/hw/ip/rv_plic
      SystemVerilog
      •
      Apache License 2.0
      •22•0•0•0•Updated Oct 12, 2023Oct 12, 2023

    • axi_riscv_atomics

      Public
      AXI Adapter(s) for RISC-V Atomic Operations
      SystemVerilog
      •
      Other
      •17•0•0•0•Updated Oct 5, 2023Oct 5, 2023

    • openhw_programs

      Public
      Documentation for the OpenHW Group's set of CORE-V RISC-V cores
      JavaScript
      •
      Other
      •97•0•0•0•Updated Aug 17, 2023Aug 17, 2023

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      SystemVerilog
      •
      Other
      •278•0•0•0•Updated Aug 11, 2023Aug 11, 2023

    • cva6_mmu_hypervisor

      Public
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      SystemVerilog
      •
      Other
      •735•0•0•0•Updated Jun 27, 2023Jun 27, 2023

    • x-heep

      Public
      C
      •92•0•0•0•Updated Dec 12, 2022Dec 12, 2022