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Example SystemVerilog output from SilverOak stage 1 #951

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Example SystemVerilog output from SilverOak stage 1 #951

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521 changes: 521 additions & 0 deletions silveroak-opentitan/aes/Impl/aes_add_round_key.sv
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138 changes: 138 additions & 0 deletions silveroak-opentitan/aes/Impl/aes_add_round_key_tb.sv
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8 changes: 8 additions & 0 deletions silveroak-opentitan/aes/Impl/aes_add_round_key_tb.tcl
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Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
open_vcd aes_add_round_key_tb.vcd
log_vcd *
log_vcd [ get_objects * ]
add_force {/aes_add_round_key_tb/clk} {0 0ns} {1 50ns} -repeat_every 100ns
run 3100ns
flush_vcd
close_vcd
exit
2,414 changes: 2,414 additions & 0 deletions silveroak-opentitan/aes/Impl/aes_add_round_key_tb.vcd
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