Bypass wide memory register #13
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Scheremo
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Scheremo
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Jul 25, 2024
Scheremo
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Scheremo
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Scheremo
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August 6, 2024 08:34
Sw: Writability and Readability test for the configuration register
Sw: Modify Bypass mem test to check different cases CI: Add support for memory bypass test
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* Hw: Add one register for bypass configuration for all clusters Sw: Writability and Readability test for the configuration register * hw: Add Register to bypass wide memory interconnect * Clear the code * Hw: Add one bypass register for each cluster Sw: Modify Bypass mem test to check different cases CI: Add support for memory bypass test --------- Co-authored-by: Lorenzo Leone <[email protected]>
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