Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Bypass wide memory register #13

Merged
merged 4 commits into from
Aug 6, 2024
+1,201 −759
Merged

Bypass wide memory register #13

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
e35fadf
Hw: Add one register for bypass configuration for all clusters
Jul 17, 2024
77ed9c6
hw: Add Register to bypass wide memory interconnect
Jul 25, 2024
c168fbc
Clear the code
Jul 25, 2024
7224f71
Hw: Add one bypass register for each cluster
Jul 25, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 3 additions & 3 deletions .gitlab/gitlab-ci.yml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,8 @@
# We initialize the nonfree repo, then spawn a sub-pipeline from it

variables:
VSIM_TESTS: '["testCluster", "testClusterOffload"]'
VSIM_TESTS: '["testCluster", "testClusterOffload", "testMemBypass"]'

stages:
- nonfree

Expand All @@ -25,7 +25,7 @@ process:
- envsubst '${VSIM_TESTS}' < nonfree/ci.yml > nonfree/processed_ci.yml
artifacts:
paths: [ nonfree/processed_ci.yml ]

subpipe:
stage: nonfree
needs: [ process ]
Expand Down
702 changes: 363 additions & 339 deletions hw/chimera_cluster_adapter.sv
View file
Open in desktop

Large diffs are not rendered by default.

777 changes: 392 additions & 385 deletions hw/chimera_top_wrapper.sv
View file
Open in desktop

Large diffs are not rendered by default.

96 changes: 68 additions & 28 deletions hw/regs/chimera_reg_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
package chimera_reg_pkg;

// Address widths within the block
parameter int BlockAw = 6;
parameter int BlockAw = 7;

////////////////////////////
// Typedefs for registers //
Expand Down Expand Up @@ -61,35 +61,65 @@ package chimera_reg_pkg;
logic q;
} chimera_reg2hw_cluster_5_clk_gate_en_reg_t;

typedef struct packed {
logic q;
} chimera_reg2hw_wide_mem_cluster_1_bypass_reg_t;

typedef struct packed {
logic q;
} chimera_reg2hw_wide_mem_cluster_2_bypass_reg_t;

typedef struct packed {
logic q;
} chimera_reg2hw_wide_mem_cluster_3_bypass_reg_t;

typedef struct packed {
logic q;
} chimera_reg2hw_wide_mem_cluster_4_bypass_reg_t;

typedef struct packed {
logic q;
} chimera_reg2hw_wide_mem_cluster_5_bypass_reg_t;

// Register -> HW type
typedef struct packed {
chimera_reg2hw_snitch_boot_addr_reg_t snitch_boot_addr; // [228:197]
chimera_reg2hw_snitch_intr_handler_addr_reg_t snitch_intr_handler_addr; // [196:165]
chimera_reg2hw_snitch_cluster_1_return_reg_t snitch_cluster_1_return; // [164:133]
chimera_reg2hw_snitch_cluster_2_return_reg_t snitch_cluster_2_return; // [132:101]
chimera_reg2hw_snitch_cluster_3_return_reg_t snitch_cluster_3_return; // [100:69]
chimera_reg2hw_snitch_cluster_4_return_reg_t snitch_cluster_4_return; // [68:37]
chimera_reg2hw_snitch_cluster_5_return_reg_t snitch_cluster_5_return; // [36:5]
chimera_reg2hw_cluster_1_clk_gate_en_reg_t cluster_1_clk_gate_en; // [4:4]
chimera_reg2hw_cluster_2_clk_gate_en_reg_t cluster_2_clk_gate_en; // [3:3]
chimera_reg2hw_cluster_3_clk_gate_en_reg_t cluster_3_clk_gate_en; // [2:2]
chimera_reg2hw_cluster_4_clk_gate_en_reg_t cluster_4_clk_gate_en; // [1:1]
chimera_reg2hw_cluster_5_clk_gate_en_reg_t cluster_5_clk_gate_en; // [0:0]
chimera_reg2hw_snitch_boot_addr_reg_t snitch_boot_addr; // [233:202]
chimera_reg2hw_snitch_intr_handler_addr_reg_t snitch_intr_handler_addr; // [201:170]
chimera_reg2hw_snitch_cluster_1_return_reg_t snitch_cluster_1_return; // [169:138]
chimera_reg2hw_snitch_cluster_2_return_reg_t snitch_cluster_2_return; // [137:106]
chimera_reg2hw_snitch_cluster_3_return_reg_t snitch_cluster_3_return; // [105:74]
chimera_reg2hw_snitch_cluster_4_return_reg_t snitch_cluster_4_return; // [73:42]
chimera_reg2hw_snitch_cluster_5_return_reg_t snitch_cluster_5_return; // [41:10]
chimera_reg2hw_cluster_1_clk_gate_en_reg_t cluster_1_clk_gate_en; // [9:9]
chimera_reg2hw_cluster_2_clk_gate_en_reg_t cluster_2_clk_gate_en; // [8:8]
chimera_reg2hw_cluster_3_clk_gate_en_reg_t cluster_3_clk_gate_en; // [7:7]
chimera_reg2hw_cluster_4_clk_gate_en_reg_t cluster_4_clk_gate_en; // [6:6]
chimera_reg2hw_cluster_5_clk_gate_en_reg_t cluster_5_clk_gate_en; // [5:5]
chimera_reg2hw_wide_mem_cluster_1_bypass_reg_t wide_mem_cluster_1_bypass; // [4:4]
chimera_reg2hw_wide_mem_cluster_2_bypass_reg_t wide_mem_cluster_2_bypass; // [3:3]
chimera_reg2hw_wide_mem_cluster_3_bypass_reg_t wide_mem_cluster_3_bypass; // [2:2]
chimera_reg2hw_wide_mem_cluster_4_bypass_reg_t wide_mem_cluster_4_bypass; // [1:1]
chimera_reg2hw_wide_mem_cluster_5_bypass_reg_t wide_mem_cluster_5_bypass; // [0:0]
} chimera_reg2hw_t;

// Register offsets
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_BOOT_ADDR_OFFSET = 6'h 0;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_INTR_HANDLER_ADDR_OFFSET = 6'h 4;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_1_RETURN_OFFSET = 6'h 8;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_2_RETURN_OFFSET = 6'h c;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_3_RETURN_OFFSET = 6'h 10;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_4_RETURN_OFFSET = 6'h 14;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_5_RETURN_OFFSET = 6'h 18;
parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_1_CLK_GATE_EN_OFFSET = 6'h 1c;
parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_2_CLK_GATE_EN_OFFSET = 6'h 20;
parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_3_CLK_GATE_EN_OFFSET = 6'h 24;
parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_4_CLK_GATE_EN_OFFSET = 6'h 28;
parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_5_CLK_GATE_EN_OFFSET = 6'h 2c;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_BOOT_ADDR_OFFSET = 7'h 0;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_INTR_HANDLER_ADDR_OFFSET = 7'h 4;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_1_RETURN_OFFSET = 7'h 8;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_2_RETURN_OFFSET = 7'h c;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_3_RETURN_OFFSET = 7'h 10;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_4_RETURN_OFFSET = 7'h 14;
parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_5_RETURN_OFFSET = 7'h 18;
parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_1_CLK_GATE_EN_OFFSET = 7'h 1c;
parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_2_CLK_GATE_EN_OFFSET = 7'h 20;
parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_3_CLK_GATE_EN_OFFSET = 7'h 24;
parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_4_CLK_GATE_EN_OFFSET = 7'h 28;
parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_5_CLK_GATE_EN_OFFSET = 7'h 2c;
parameter logic [BlockAw-1:0] CHIMERA_WIDE_MEM_CLUSTER_1_BYPASS_OFFSET = 7'h 30;
parameter logic [BlockAw-1:0] CHIMERA_WIDE_MEM_CLUSTER_2_BYPASS_OFFSET = 7'h 34;
parameter logic [BlockAw-1:0] CHIMERA_WIDE_MEM_CLUSTER_3_BYPASS_OFFSET = 7'h 38;
parameter logic [BlockAw-1:0] CHIMERA_WIDE_MEM_CLUSTER_4_BYPASS_OFFSET = 7'h 3c;
parameter logic [BlockAw-1:0] CHIMERA_WIDE_MEM_CLUSTER_5_BYPASS_OFFSET = 7'h 40;

// Register index
typedef enum int {
Expand All @@ -104,11 +134,16 @@ package chimera_reg_pkg;
CHIMERA_CLUSTER_2_CLK_GATE_EN,
CHIMERA_CLUSTER_3_CLK_GATE_EN,
CHIMERA_CLUSTER_4_CLK_GATE_EN,
CHIMERA_CLUSTER_5_CLK_GATE_EN
CHIMERA_CLUSTER_5_CLK_GATE_EN,
CHIMERA_WIDE_MEM_CLUSTER_1_BYPASS,
CHIMERA_WIDE_MEM_CLUSTER_2_BYPASS,
CHIMERA_WIDE_MEM_CLUSTER_3_BYPASS,
CHIMERA_WIDE_MEM_CLUSTER_4_BYPASS,
CHIMERA_WIDE_MEM_CLUSTER_5_BYPASS
} chimera_id_e;

// Register width information to check illegal writes
parameter logic [3:0] CHIMERA_PERMIT [12] = '{
parameter logic [3:0] CHIMERA_PERMIT [17] = '{
4'b 1111, // index[ 0] CHIMERA_SNITCH_BOOT_ADDR
4'b 1111, // index[ 1] CHIMERA_SNITCH_INTR_HANDLER_ADDR
4'b 1111, // index[ 2] CHIMERA_SNITCH_CLUSTER_1_RETURN
Expand All @@ -120,7 +155,12 @@ package chimera_reg_pkg;
4'b 0001, // index[ 8] CHIMERA_CLUSTER_2_CLK_GATE_EN
4'b 0001, // index[ 9] CHIMERA_CLUSTER_3_CLK_GATE_EN
4'b 0001, // index[10] CHIMERA_CLUSTER_4_CLK_GATE_EN
4'b 0001 // index[11] CHIMERA_CLUSTER_5_CLK_GATE_EN
4'b 0001, // index[11] CHIMERA_CLUSTER_5_CLK_GATE_EN
4'b 0001, // index[12] CHIMERA_WIDE_MEM_CLUSTER_1_BYPASS
4'b 0001, // index[13] CHIMERA_WIDE_MEM_CLUSTER_2_BYPASS
4'b 0001, // index[14] CHIMERA_WIDE_MEM_CLUSTER_3_BYPASS
4'b 0001, // index[15] CHIMERA_WIDE_MEM_CLUSTER_4_BYPASS
4'b 0001 // index[16] CHIMERA_WIDE_MEM_CLUSTER_5_BYPASS
};

endpackage
Expand Down
Loading
Loading