ALU completed, testbed finished, all tests passed.

scarter93 · Jan 31, 2016 · bfe5b19 · bfe5b19
1 parent 2ceeda3
commit bfe5b19
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Showing 14 changed files with 2,131 additions and 247 deletions.
diff --git a/alu_16.vhd b/alu_16.vhd
@@ -94,12 +94,10 @@ Process(CLOCK, RESET)
 					output <= shift_right(input1, to_integer(unsigned(input2)));
 					out_code <= in_code;
 				when LSL =>
-					input1_temp <= std_logic_vector(input1);
-					output <= signed(shift_left(unsigned(input1_temp), to_integer(unsigned(input2))));
+					output <= signed(shift_left(unsigned(std_logic_vector(input1)), to_integer(unsigned(input2))));
 					out_code <= in_code;
 				when LSR =>
-					input1_temp <= std_logic_vector(input1);
-					output <= signed(shift_right(unsigned(input1_temp), to_integer(unsigned(input2))));
+					output <= signed(shift_right(unsigned(std_logic_vector(input1)), to_integer(unsigned(input2))));
 					out_code <= in_code;
 				when others =>
 					output <= "0000000000000000";

diff --git a/alu_16.vhd.bak b/alu_16.vhd.bak
@@ -29,7 +29,7 @@ architecture implementation of alu_16 is
 CONSTANT ADD : unsigned(3 downto 0) := "0000";
 CONSTANT SUB : unsigned(3 downto 0) := "0001";
 CONSTANT NOT_IN : unsigned(3 downto 0) := "0010";
-CONSTANT ADD_IN : unsigned(3 downto 0) := "0011";
+CONSTANT AND_IN : unsigned(3 downto 0) := "0011";
 CONSTANT NAND_IN : unsigned(3 downto 0) := "0100";
 CONSTANT OR_IN : unsigned(3 downto 0) := "0101";
 CONSTANT NOR_IN : unsigned(3 downto 0) := "0110";
@@ -94,12 +94,12 @@ Process(CLOCK, RESET)
 					output <= shift_right(input1, to_integer(unsigned(input2)));
 					out_code <= in_code;
 				when LSL =>
-					input1_temp <= std_logic_vector(input1);
-					output <= signed(shift_left(unsigned(input1_temp), to_integer(unsigned(input2))));
+					--input1_temp <= std_logic_vector(input1);
+					output <= signed(shift_left(unsigned(std_logic_vector(input1)), to_integer(unsigned(input2))));
 					out_code <= in_code;
 				when LSR =>
-					input1_temp <= std_logic_vector(input1);
-					output <= signed(shift_right(unsigned(input1_temp), to_integer(unsigned(input2))));
+					--input1_temp <= std_logic_vector(input1);
+					output <= signed(shift_right(unsigned(std_logic_vector(input1)), to_integer(unsigned(input2))));
 					out_code <= in_code;
 				when others =>
 					output <= "0000000000000000";

diff --git a/alu_tb.tcl b/alu_tb.tcl
@@ -0,0 +1,30 @@
+proc AddWaves {} {
+	;#Add waves we're interested in to the Wave window
+    add wave -position end sim:/alu_tb/opcode_t
+    add wave -position end sim:/alu_tb/input1_t
+    add wave -position end sim:/alu_tb/input2_t
+    add wave -position end sim:/alu_tb/clk
+    add wave -position end sim:/alu_tb/reset_t
+    add wave -position end sim:/alu_tb/output_t
+    add wave -position end sim:/alu_tb/status_t
+}
+
+vlib work
+
+;# Compile components if any
+vcom alu_16.vhd
+vcom alu_tb.vhd
+
+;# Start simulation
+vsim alu_tb
+
+;# Add the waves
+
+AddWaves
+
+;# Generate a clock with 1ns period
+force -deposit clk 0 0 ns, 1 0.5 ns -repeat 1 ns
+
+
+;# Run for 50 ns
+run 50ns