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7 Open 0 Closed
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Issues list

Cell is placed inside reconfig block
#7 opened Mar 1, 2023 by hoangvm97
1
Compile with normal flow (no partial reconfig) error
#6 opened Mar 1, 2023 by hoangvm97
Add RPU and interface count readbacks to the FPGA image enhancement New feature or request
#5 opened Feb 11, 2023 by mkhazraee
Update PCIe modules to support straddling enhancement New feature or request
#4 opened Nov 23, 2022 by mkhazraee
Testbenches insert packets at higher rate than 100Gbps per interface enhancement New feature or request
#3 opened Nov 15, 2022 by mkhazraee
Very rarely a slot is returned to the LB which was supposed to be in LB and not the RPUs. bug Something isn't working enhancement New feature or request
#2 opened Nov 15, 2022 by mkhazraee
1
Adjust when to drop packets per incoming interface for the RR scheduler bug Something isn't working enhancement New feature or request
#1 opened Nov 15, 2022 by mkhazraee
1
ProTip! Follow long discussions with comments:>50.