Merge pull request #831 from saurabhsingh-pvips/new_rv64i

[PyFlow]: Add support for RV64IMC

pygen/pygen_src/isa/riscv_instr.py

@@ -90,6 +90,7 @@ def __init__(self):
         self.has_rd = 1
         self.has_imm = 1
         self.shift_t = vsc.uint32_t(0xffffffff)
+        self.mask = 32
         self.XLEN = vsc.uint32_t(32)  # XLEN is used in constraint throughout the generator.
         # Hence, XLEN should be of PyVSC type in order to use it in a constraint block
         self.XLEN = rcs.XLEN
@@ -525,8 +526,8 @@ def update_imm_str(self):
         self.imm_str = str(self.uintToInt(self.imm))
 
     def uintToInt(self, x):
-        if x < (2 ** rcs.XLEN) / 2:
+        if x < (2 ** self.mask) / 2:
             signed_x = x
         else:
-            signed_x = x - 2 ** rcs.XLEN
+            signed_x = x - 2 ** self.mask
         return signed_x

pygen/pygen_src/isa/rv64c_instr.py

@@ -0,0 +1,33 @@
+"""
+Copyright 2020 Google LLC
+Copyright 2020 PerfectVIPs Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+http://www.apache.org/licenses/LICENSE-2.0
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
+"""
+
+from pygen_src.riscv_defines import DEFINE_C_INSTR
+from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t,
+                                       riscv_instr_category_t, riscv_instr_group_t)
+
+
+DEFINE_C_INSTR(riscv_instr_name_t.C_ADDIW, riscv_instr_format_t.CI_FORMAT,
+               riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64C, g=globals())
+DEFINE_C_INSTR(riscv_instr_name_t.C_SUBW, riscv_instr_format_t.CA_FORMAT,
+               riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64C, g=globals())
+DEFINE_C_INSTR(riscv_instr_name_t.C_ADDW, riscv_instr_format_t.CA_FORMAT,
+               riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64C, g=globals())
+DEFINE_C_INSTR(riscv_instr_name_t.C_LD, riscv_instr_format_t.CL_FORMAT,
+               riscv_instr_category_t.LOAD, riscv_instr_group_t.RV64C, g=globals())
+DEFINE_C_INSTR(riscv_instr_name_t.C_SD, riscv_instr_format_t.CS_FORMAT,
+               riscv_instr_category_t.STORE, riscv_instr_group_t.RV64C, g=globals())
+DEFINE_C_INSTR(riscv_instr_name_t.C_LDSP, riscv_instr_format_t.CI_FORMAT,
+               riscv_instr_category_t.LOAD, riscv_instr_group_t.RV64C, g=globals())
+DEFINE_C_INSTR(riscv_instr_name_t.C_SDSP, riscv_instr_format_t.CSS_FORMAT,
+               riscv_instr_category_t.STORE, riscv_instr_group_t.RV64C, g=globals())

pygen/pygen_src/isa/rv64i_instr.py

@@ -0,0 +1,45 @@
+"""
+Copyright 2020 Google LLC
+Copyright 2020 PerfectVIPs Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+http://www.apache.org/licenses/LICENSE-2.0
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
+"""
+
+from pygen_src.riscv_defines import DEFINE_INSTR
+from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t,
+                                       riscv_instr_category_t, riscv_instr_group_t)
+
+
+DEFINE_INSTR(riscv_instr_name_t.LWU, riscv_instr_format_t.I_FORMAT,
+             riscv_instr_category_t.LOAD, riscv_instr_group_t.RV64I, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.LD, riscv_instr_format_t.I_FORMAT,
+             riscv_instr_category_t.LOAD, riscv_instr_group_t.RV64I, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.SD, riscv_instr_format_t.S_FORMAT,
+             riscv_instr_category_t.STORE, riscv_instr_group_t.RV64I, g=globals())
+# SHIFT intructions
+DEFINE_INSTR(riscv_instr_name_t.SLLW, riscv_instr_format_t.R_FORMAT,
+             riscv_instr_category_t.SHIFT, riscv_instr_group_t.RV64I, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.SLLIW, riscv_instr_format_t.I_FORMAT,
+             riscv_instr_category_t.SHIFT, riscv_instr_group_t.RV64I, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.SRLW, riscv_instr_format_t.R_FORMAT,
+             riscv_instr_category_t.SHIFT, riscv_instr_group_t.RV64I, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.SRLIW, riscv_instr_format_t.I_FORMAT,
+             riscv_instr_category_t.SHIFT, riscv_instr_group_t.RV64I, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.SRAW, riscv_instr_format_t.R_FORMAT,
+             riscv_instr_category_t.SHIFT, riscv_instr_group_t.RV64I, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.SRAIW, riscv_instr_format_t.I_FORMAT,
+             riscv_instr_category_t.SHIFT, riscv_instr_group_t.RV64I, g=globals())
+# ARITHMETIC intructions
+DEFINE_INSTR(riscv_instr_name_t.ADDW, riscv_instr_format_t.R_FORMAT,
+             riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64I, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.ADDIW, riscv_instr_format_t.I_FORMAT,
+             riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64I, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.SUBW, riscv_instr_format_t.R_FORMAT,
+             riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64I, g=globals())

pygen/pygen_src/isa/rv64m_instr.py

@@ -0,0 +1,29 @@
+"""
+Copyright 2020 Google LLC
+Copyright 2020 PerfectVIPs Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+http://www.apache.org/licenses/LICENSE-2.0
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
+"""
+
+from pygen_src.riscv_defines import DEFINE_INSTR
+from pygen_src.riscv_instr_pkg import (riscv_instr_name_t, riscv_instr_format_t,
+                                       riscv_instr_category_t, riscv_instr_group_t)
+
+
+DEFINE_INSTR(riscv_instr_name_t.MULW, riscv_instr_format_t.R_FORMAT,
+             riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.DIVW, riscv_instr_format_t.R_FORMAT,
+             riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.DIVUW, riscv_instr_format_t.R_FORMAT,
+             riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.REMW, riscv_instr_format_t.R_FORMAT,
+             riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals())
+DEFINE_INSTR(riscv_instr_name_t.REMUW, riscv_instr_format_t.R_FORMAT,
+             riscv_instr_category_t.ARITHMETIC, riscv_instr_group_t.RV64M, g=globals())

pygen/pygen_src/target/rv64imc/riscv_core_setting.py

@@ -0,0 +1,119 @@
+"""
+Copyright 2020 Google LLC
+Copyright 2020 PerfectVIPs Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+http://www.apache.org/licenses/LICENSE-2.0
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+"""
+
+import math
+from pygen_src.riscv_instr_pkg import (privileged_reg_t, satp_mode_t,
+                                       riscv_instr_group_t, mtvec_mode_t,
+                                       privileged_mode_t)
+
+
+# -----------------------------------------------------------------------------
+# Processor feature configuration
+# -----------------------------------------------------------------------------
+
+# XLEN
+XLEN = 64
+
+# set to BARE if address translation is not supported
+SATP_MODE = satp_mode_t.BARE
+
+# Supported Privileged mode
+supported_privileged_mode = [privileged_mode_t.MACHINE_MODE]
+
+# Unsupported instructions
+unsupported_instr = []
+
+# ISA supported by the processor
+supported_isa = [riscv_instr_group_t.RV32I, riscv_instr_group_t.RV32M,
+                 riscv_instr_group_t.RV32C, riscv_instr_group_t.RV64I,
+                 riscv_instr_group_t.RV64M, riscv_instr_group_t.RV64C]
+
+# Interrupt mode support
+supported_interrupt_mode = [mtvec_mode_t.DIRECT, mtvec_mode_t.VECTORED]
+
+# The number of interrupt vectors to be generated, only used if VECTORED
+# interrupt mode is supported
+max_interrupt_vector_num = 16
+
+# Physical memory protection support
+support_pmp = 0
+
+# Debug mode support
+support_debug_mode = 0
+
+# Support delegate trap to user mode
+support_umode_trap = 0
+
+# Support sfence.vma instruction
+support_sfence = 0
+
+# Support unaligned load/store
+support_unaligned_load_store = 1
+
+# GPR Setting
+NUM_FLOAT_GPR = 32
+NUM_GPR = 32
+NUM_VEC_GPR = 32
+
+# -----------------------------------------------------------------------------
+# Vector extension configuration
+# -----------------------------------------------------------------------------
+
+# Parameter for vector extension
+VECTOR_EXTENSION_ENABLE = 0
+
+VLEN = 512
+
+# Maximum size of a single vector element
+ELEN = 32
+
+# Minimum size of a sub-element, which must be at most 8-bits.
+SELEN = 8
+
+# Maximum size of a single vector element (encoded in vsew format)
+VELEN = int(math.log(ELEN) // math.log(2)) - 3
+
+# Maxium LMUL supported by the core
+MAX_LMUL = 8
+
+
+# -----------------------------------------------------------------------------
+# Multi-harts configuration
+# -----------------------------------------------------------------------------
+
+# Number of harts
+NUM_HARTS = 1
+
+# -----------------------------------------------------------------------------
+# Previleged CSR implementation
+# -----------------------------------------------------------------------------
+
+# Implemented previlieged CSR list
+implemented_csr = [privileged_reg_t.MVENDORID,  # Vendor ID
+                   privileged_reg_t.MARCHID,  # Architecture ID
+                   privileged_reg_t.MIMPID,  # Implementation ID
+                   privileged_reg_t.MHARTID,  # Hardware thread ID
+                   privileged_reg_t.MSTATUS,  # Machine status
+                   privileged_reg_t.MISA,  # ISA and extensions
+                   privileged_reg_t.MIE,  # Machine interrupt-enable register
+                   privileged_reg_t.MTVEC,  # Machine trap-handler base address
+                   privileged_reg_t.MCOUNTEREN,  # Machine counter enable
+                   privileged_reg_t.MSCRATCH,  # Scratch register for machine trap handlers
+                   privileged_reg_t.MEPC,  # Machine exception program counter
+                   privileged_reg_t.MCAUSE,  # Machine trap cause
+                   privileged_reg_t.MTVAL,  # Machine bad address or instruction
+                   privileged_reg_t.MIP  # Machine interrupt pending
+                   ]
+
+# Implementation-specific custom CSRs
+custom_csr = []